\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
IWDG Control Command Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : ADC Enable
bits : 0 - 7 (8 bit)
access : read-write
IWDG Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDGOVF : ADC_Channel 1 Result
bits : 0 - 0 (1 bit)
access : read-only
IWDG Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDGINTCLR : ADC Channel 3 Result
bits : 0 - 0 (1 bit)
access : write-only
IWDG register Writer Protect
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDGREN : ADC Channel 3 Result
bits : 0 - 0 (1 bit)
access : read-write
IWDG Config Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDGMODE : ADC Convect Auto Triger 0
bits : 0 - 0 (1 bit)
access : read-write
IWDGINTMSK : ADC Convect Auto Triger 1
bits : 1 - 1 (1 bit)
access : read-write
IWDGRUNF : ADC_Convect mode Select
bits : 2 - 2 (1 bit)
access : read-only
Count ReLoad Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDGRLOAD : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 19 (20 bit)
access : read-write
Count Value
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IWDGCNT : ADC Channel 0 Result
bits : 0 - 19 (20 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.