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LPTIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

CNTVAL

INTCLR

BGLOAD

CR

LOAD

INTSR


CNTVAL

Low Power Count Read_Only Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTVAL CNTVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPT_CNT

LPT_CNT : ADC Enable
bits : 0 - 0 (1 bit)
access : read-only


INTCLR

LPTIM Interrupt Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLR

ICLR : ADC_Channel 1 Result
bits : 0 - 0 (1 bit)
access : write-only


BGLOAD

LPTIM Circle reload Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGLOAD BGLOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BGLOAD

BGLOAD : ADC Channel 3 Result
bits : 0 - 15 (16 bit)
access : read-write


CR

LPTIM Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM_RUN MODE CT_SEL TOG_EN TCK_SEL GATE_EN GATE_P INT_EN TCK_EN WT_FLAG

TIM_RUN : ADC Convect Auto Triger 0
bits : 0 - 0 (1 bit)
access : read-write

MODE : ADC Convect Auto Triger 1
bits : 1 - 1 (1 bit)
access : read-write

CT_SEL : ADC_Convect mode Select
bits : 2 - 2 (1 bit)
access : read-write

TOG_EN : ADC_Convect Result Auto ADD
bits : 3 - 3 (1 bit)
access : read-write

TCK_SEL : ADC_Low threshold Compare Control
bits : 4 - 5 (2 bit)
access : read-write

GATE_EN : ADC_High threshold Compare Control
bits : 6 - 6 (1 bit)
access : read-write

GATE_P : ADC_Area Compare Control
bits : 7 - 7 (1 bit)
access : read-write

INT_EN : ADC_Convect Result register Clear
bits : 8 - 8 (1 bit)
access : read-write

TCK_EN : ADC_Convect Result register Clear
bits : 9 - 9 (1 bit)
access : read-write

WT_FLAG : ADC_Convect Result register Clear
bits : 16 - 16 (1 bit)
access : read-write


LOAD

LPTIM Reload Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOAD LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOAD

LOAD : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 15 (16 bit)
access : read-write


INTSR

LPTIM Interrupt Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSR INTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTF

INTF : interrupt flag
bits : 0 - 0 (1 bit)
access : read-only



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