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BASETIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

CR

MSKINTSR

INTCLR

BGLOAD

LOAD

CNT

RAWINTSR


CR

TIM10 Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR_PRSC ONESHOT TMR_SIZE INTEN MODE TR CT_SEL TOG_EN GATE_EN GATE_P

TMR_PRSC : ADC Enable
bits : 0 - 2 (3 bit)
access : read-write

ONESHOT : ADC_ Start Control
bits : 3 - 3 (1 bit)
access : read-write

TMR_SIZE : ADC Clock Select
bits : 4 - 4 (1 bit)
access : read-write

INTEN : ADC Channel Select
bits : 5 - 5 (1 bit)
access : read-write

MODE : ADC Sample Circle Select
bits : 6 - 6 (1 bit)
access : read-write

TR : ADC Continue Convert Status Control
bits : 7 - 7 (1 bit)
access : read-write

CT_SEL : ADC Continue Convert Status Control
bits : 8 - 8 (1 bit)
access : read-write

TOG_EN : ADC Continue Convert Status Control
bits : 9 - 9 (1 bit)
access : read-write

GATE_EN : ADC Continue Convert Status Control
bits : 10 - 10 (1 bit)
access : read-write

GATE_P : ADC Continue Convert Status Control
bits : 11 - 11 (1 bit)
access : read-write


MSKINTSR

Read Interrupt Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSKINTSR MSKINTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF

TF : ADC_Channel 1 Result
bits : 0 - 0 (1 bit)
access : read-only


INTCLR

Interrupt Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTCLR

INTCLR : ADC_Channel 2 Result
bits : 0 - 0 (1 bit)
access : write-only


BGLOAD

32Bits Circles Reload Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BGLOAD BGLOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BGLOAD

BGLOAD : ADC Channel 3 Result
bits : 0 - 31 (32 bit)
access : read-write


LOAD

32bits Auto Load Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOAD LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOAD

LOAD : ADC Convect Auto Triger 0
bits : 0 - 31 (32 bit)
access : read-write


CNT

Read Count Register，Only Read
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 31 (32 bit)
access : read-only


RAWINTSR

READ Orignal Interrupt Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAWINTSR RAWINTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIS

RIS : ADC Channel 0 Result
bits : 0 - 0 (1 bit)
access : read-only



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