\n
address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection :
TIM1 Control Register1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Enable
bits : 0 - 0 (1 bit)
access : read-write
UDIS : Update Disable
bits : 1 - 1 (1 bit)
access : read-write
URS : Update Request Source
bits : 2 - 2 (1 bit)
access : read-write
OPM : One Pulse Mode
bits : 3 - 3 (1 bit)
access : read-write
DIR : Direction
bits : 4 - 4 (1 bit)
access : read-write
CMS : Center
bits : 5 - 6 (2 bit)
access : read-write
ARPE : Auto
bits : 7 - 7 (1 bit)
access : read-write
CKD : Auto
bits : 8 - 9 (2 bit)
access : read-write
TIM1 Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIF : ADC_Channel 1 Result
bits : 0 - 0 (1 bit)
access : read-write
CC1IF : ADC_Channel 1 Result
bits : 1 - 1 (1 bit)
access : read-write
CC2IF : ADC_Channel 1 Result
bits : 2 - 2 (1 bit)
access : read-write
CC3IF : ADC_Channel 1 Result
bits : 3 - 3 (1 bit)
access : read-write
CC4IF : ADC_Channel 1 Result
bits : 4 - 4 (1 bit)
access : read-write
COMIF : ADC_Channel 1 Result
bits : 5 - 5 (1 bit)
access : read-write
TIF : ADC_Channel 1 Result
bits : 6 - 6 (1 bit)
access : read-write
BIF : ADC_Channel 1 Result
bits : 7 - 7 (1 bit)
access : read-write
CC1OF : ADC_Channel 1 Result
bits : 9 - 9 (1 bit)
access : read-write
CC2OF : ADC_Channel 1 Result
bits : 10 - 10 (1 bit)
access : read-write
CC3OF : ADC_Channel 1 Result
bits : 11 - 11 (1 bit)
access : read-write
CC4OF : ADC_Channel 1 Result
bits : 12 - 12 (1 bit)
access : read-write
TIM1 Event Trig Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UG : ADC_Channel 2 Result
bits : 0 - 0 (1 bit)
access : write-only
CC1G : ADC_Channel 2 Result
bits : 1 - 1 (1 bit)
access : write-only
CC2G : ADC_Channel 2 Result
bits : 2 - 2 (1 bit)
access : write-only
CC3G : ADC_Channel 2 Result
bits : 3 - 3 (1 bit)
access : write-only
CC4G : ADC_Channel 2 Result
bits : 4 - 4 (1 bit)
access : write-only
COMG : ADC_Channel 2 Result
bits : 5 - 5 (1 bit)
access : write-only
TG : ADC_Channel 2 Result
bits : 6 - 6 (1 bit)
access : write-only
BG : ADC_Channel 2 Result
bits : 7 - 7 (1 bit)
access : write-only
TIM1 Capture/Compare Mode Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1S : ADC Channel 3 Result
bits : 0 - 1 (2 bit)
access : read-write
OC1FE : ADC Channel 3 Result
bits : 2 - 2 (1 bit)
access : read-write
OC1PE : ADC Channel 3 Result
bits : 3 - 3 (1 bit)
access : read-write
OC1M : ADC Channel 3 Result
bits : 4 - 6 (3 bit)
access : read-write
OC1CE : ADC Channel 3 Result
bits : 7 - 7 (1 bit)
access : read-write
CC2S : ADC Channel 3 Result
bits : 8 - 9 (2 bit)
access : read-write
OC2FE : ADC Channel 3 Result
bits : 10 - 10 (1 bit)
access : read-write
OC2PE : ADC Channel 3 Result
bits : 11 - 11 (1 bit)
access : read-write
OC2M : ADC Channel 3 Result
bits : 12 - 14 (3 bit)
access : read-write
OC2CE : ADC Channel 3 Result
bits : 15 - 15 (1 bit)
access : read-write
TIM1 Capture/Compare Mode Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC3S : ADC_Channel 4 Result
bits : 0 - 1 (2 bit)
access : read-only
OC3FE : ADC_Channel 4 Result
bits : 2 - 2 (1 bit)
access : read-only
OC3PE : ADC_Channel 4 Result
bits : 3 - 3 (1 bit)
access : read-only
OC3M : ADC_Channel 4 Result
bits : 4 - 6 (3 bit)
access : read-only
OC3CE : ADC_Channel 4 Result
bits : 7 - 7 (1 bit)
access : read-only
CC4S : ADC_Channel 4 Result
bits : 8 - 9 (2 bit)
access : read-only
OC4FE : ADC_Channel 4 Result
bits : 10 - 10 (1 bit)
access : read-only
OC4PE : ADC_Channel 4 Result
bits : 11 - 11 (1 bit)
access : read-only
OC4M : ADC_Channel 4 Result
bits : 12 - 14 (3 bit)
access : read-only
OC4CE : ADC_Channel 4 Result
bits : 15 - 15 (1 bit)
access : read-only
TIM1 Captuer/Compare Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC1E : ADC_Channel 5 Result
bits : 0 - 0 (1 bit)
access : read-write
CC1P : ADC_Channel 5 Result
bits : 1 - 1 (1 bit)
access : read-write
CC1NE : ADC_Channel 5 Result
bits : 2 - 2 (1 bit)
access : read-write
CC1NP : ADC_Channel 5 Result
bits : 3 - 3 (1 bit)
access : read-write
CC2E : ADC_Channel 5 Result
bits : 4 - 4 (1 bit)
access : read-write
CC2P : ADC_Channel 5 Result
bits : 5 - 5 (1 bit)
access : read-write
CC2NE : ADC_Channel 5 Result
bits : 6 - 6 (1 bit)
access : read-write
CC2NP : ADC_Channel 5 Result
bits : 7 - 7 (1 bit)
access : read-write
CC3E : ADC_Channel 5 Result
bits : 8 - 8 (1 bit)
access : read-write
CC3P : ADC_Channel 5 Result
bits : 9 - 9 (1 bit)
access : read-write
CC3NE : ADC_Channel 5 Result
bits : 10 - 10 (1 bit)
access : read-write
CC3NP : ADC_Channel 5 Result
bits : 11 - 11 (1 bit)
access : read-write
CC4E : ADC_Channel 5 Result
bits : 12 - 12 (1 bit)
access : read-write
CC4P : ADC_Channel 5 Result
bits : 13 - 13 (1 bit)
access : read-write
TIM1 Count
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : ADC_Channel 6 Result
bits : 0 - 15 (16 bit)
access : read-only
TIM1 Prescale Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : ADC_Channel 7 Result
bits : 0 - 15 (16 bit)
access : read-write
TIM1 Auto Load Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARR : ADC_ Result
bits : 0 - 15 (16 bit)
access : read-write
TIM1 Repeate Count Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP : ADC_Convect Result Compare High Therashold
bits : 0 - 7 (8 bit)
access : read-write
Captuer/Compare Register1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR1 : ADC Convect Result Compare High threshold
bits : 0 - 15 (16 bit)
access : read-write
Capture/Compare Register2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR2 : ADC_Convect Result Compare Low Threshold
bits : 0 - 15 (16 bit)
access : read-only
Capture/Compare Register3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR3 : ADC Channel 7~0 Interrupt Mask Config
bits : 0 - 15 (16 bit)
access : read-write
TIM1 Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCPC : ADC Convect Auto Triger 0
bits : 0 - 0 (1 bit)
access : read-write
CCUS : ADC Convect Auto Triger 1
bits : 2 - 2 (1 bit)
access : read-write
MMS : ADC_Convect mode Select
bits : 4 - 6 (3 bit)
access : read-write
TI1S : ADC_Convect Result Auto ADD
bits : 7 - 7 (1 bit)
access : read-write
OIS1 : ADC_Low threshold Compare Control
bits : 8 - 8 (1 bit)
access : read-write
OIS1N : ADC_High threshold Compare Control
bits : 9 - 9 (1 bit)
access : read-write
OIS2 : ADC_Area Compare Control
bits : 10 - 10 (1 bit)
access : read-write
OIS2N : ADC_Convect Result register Clear
bits : 11 - 11 (1 bit)
access : read-write
OIS3 : ADC_Convect Result register Clear
bits : 12 - 12 (1 bit)
access : read-write
OIS3N : ADC_Convect Result register Clear
bits : 13 - 13 (1 bit)
access : read-write
OIS4 : ADC_Convect Result register Clear
bits : 14 - 14 (1 bit)
access : read-write
TIM1 Capture/Compare Register4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCR4 : Reload value to use for 10ms timing
bits : 0 - 15 (16 bit)
access : read-write
TIM1 Brush and DEAD Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTG : Reload value to use for 10ms timing
bits : 0 - 7 (8 bit)
access : read-write
LOCK : LLT
bits : 8 - 9 (2 bit)
access : read-write
OSSI : HHT
bits : 10 - 10 (1 bit)
access : read-write
OSSR : REG
bits : 11 - 11 (1 bit)
access : read-write
BKE : CON
bits : 12 - 12 (1 bit)
access : read-write
BKP : CON
bits : 13 - 13 (1 bit)
access : read-write
AOE : CON
bits : 14 - 14 (1 bit)
access : read-write
MOE : CON
bits : 15 - 15 (1 bit)
access : read-write
TIM1 Slave mode Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMS : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 2 (3 bit)
access : read-write
TS : ADC Continue Convect Times Config
bits : 4 - 6 (3 bit)
access : read-write
MSM : ADC Convect Rounte Mode Select
bits : 7 - 7 (1 bit)
access : read-write
ETF : ADC Convect Rounte Mode Select
bits : 8 - 11 (4 bit)
access : read-write
ETPS : ADC Convect Rounte Mode Select
bits : 12 - 13 (2 bit)
access : read-write
ECE : ADC Convect Rounte Mode Select
bits : 14 - 14 (1 bit)
access : read-write
ETP : ADC Convect Rounte Mode Select
bits : 15 - 15 (1 bit)
access : read-write
TIM1 Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UIE : ADC Channel 0 Result
bits : 0 - 0 (1 bit)
access : read-write
CC1IE : ADC Channel 0 Result
bits : 1 - 1 (1 bit)
access : read-write
CC2IE : ADC Channel 0 Result
bits : 2 - 2 (1 bit)
access : read-write
CC3IE : ADC Channel 0 Result
bits : 3 - 3 (1 bit)
access : read-write
CC4IE : ADC Channel 0 Result
bits : 4 - 4 (1 bit)
access : read-write
COMIE : ADC Channel 0 Result
bits : 5 - 5 (1 bit)
access : read-write
TIE : ADC Channel 0 Result
bits : 6 - 6 (1 bit)
access : read-write
BIE : ADC Channel 0 Result
bits : 7 - 7 (1 bit)
access : read-write
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