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ADVTIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection :

Registers

CR1

SR

EGR

CCMR1

CCMR2

CCER

CNT

PSC

ARR

RCR

CCR1

CCR2

CCR3

CR2

CCR4

BDTR

SMCR

DIER


CR1

TIM1 Control Register1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM DIR CMS ARPE CKD

CEN : Enable
bits : 0 - 0 (1 bit)
access : read-write

UDIS : Update Disable
bits : 1 - 1 (1 bit)
access : read-write

URS : Update Request Source
bits : 2 - 2 (1 bit)
access : read-write

OPM : One Pulse Mode
bits : 3 - 3 (1 bit)
access : read-write

DIR : Direction
bits : 4 - 4 (1 bit)
access : read-write

CMS : Center
bits : 5 - 6 (2 bit)
access : read-write

ARPE : Auto
bits : 7 - 7 (1 bit)
access : read-write

CKD : Auto
bits : 8 - 9 (2 bit)
access : read-write


SR

TIM1 Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC2IF CC3IF CC4IF COMIF TIF BIF CC1OF CC2OF CC3OF CC4OF

UIF : ADC_Channel 1 Result
bits : 0 - 0 (1 bit)
access : read-write

CC1IF : ADC_Channel 1 Result
bits : 1 - 1 (1 bit)
access : read-write

CC2IF : ADC_Channel 1 Result
bits : 2 - 2 (1 bit)
access : read-write

CC3IF : ADC_Channel 1 Result
bits : 3 - 3 (1 bit)
access : read-write

CC4IF : ADC_Channel 1 Result
bits : 4 - 4 (1 bit)
access : read-write

COMIF : ADC_Channel 1 Result
bits : 5 - 5 (1 bit)
access : read-write

TIF : ADC_Channel 1 Result
bits : 6 - 6 (1 bit)
access : read-write

BIF : ADC_Channel 1 Result
bits : 7 - 7 (1 bit)
access : read-write

CC1OF : ADC_Channel 1 Result
bits : 9 - 9 (1 bit)
access : read-write

CC2OF : ADC_Channel 1 Result
bits : 10 - 10 (1 bit)
access : read-write

CC3OF : ADC_Channel 1 Result
bits : 11 - 11 (1 bit)
access : read-write

CC4OF : ADC_Channel 1 Result
bits : 12 - 12 (1 bit)
access : read-write


EGR

TIM1 Event Trig Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EGR EGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G CC2G CC3G CC4G COMG TG BG

UG : ADC_Channel 2 Result
bits : 0 - 0 (1 bit)
access : write-only

CC1G : ADC_Channel 2 Result
bits : 1 - 1 (1 bit)
access : write-only

CC2G : ADC_Channel 2 Result
bits : 2 - 2 (1 bit)
access : write-only

CC3G : ADC_Channel 2 Result
bits : 3 - 3 (1 bit)
access : write-only

CC4G : ADC_Channel 2 Result
bits : 4 - 4 (1 bit)
access : write-only

COMG : ADC_Channel 2 Result
bits : 5 - 5 (1 bit)
access : write-only

TG : ADC_Channel 2 Result
bits : 6 - 6 (1 bit)
access : write-only

BG : ADC_Channel 2 Result
bits : 7 - 7 (1 bit)
access : write-only


CCMR1

TIM1 Capture/Compare Mode Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMR1 CCMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S OC1FE OC1PE OC1M OC1CE CC2S OC2FE OC2PE OC2M OC2CE

CC1S : ADC Channel 3 Result
bits : 0 - 1 (2 bit)
access : read-write

OC1FE : ADC Channel 3 Result
bits : 2 - 2 (1 bit)
access : read-write

OC1PE : ADC Channel 3 Result
bits : 3 - 3 (1 bit)
access : read-write

OC1M : ADC Channel 3 Result
bits : 4 - 6 (3 bit)
access : read-write

OC1CE : ADC Channel 3 Result
bits : 7 - 7 (1 bit)
access : read-write

CC2S : ADC Channel 3 Result
bits : 8 - 9 (2 bit)
access : read-write

OC2FE : ADC Channel 3 Result
bits : 10 - 10 (1 bit)
access : read-write

OC2PE : ADC Channel 3 Result
bits : 11 - 11 (1 bit)
access : read-write

OC2M : ADC Channel 3 Result
bits : 12 - 14 (3 bit)
access : read-write

OC2CE : ADC Channel 3 Result
bits : 15 - 15 (1 bit)
access : read-write


CCMR2

TIM1 Capture/Compare Mode Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMR2 CCMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3S OC3FE OC3PE OC3M OC3CE CC4S OC4FE OC4PE OC4M OC4CE

CC3S : ADC_Channel 4 Result
bits : 0 - 1 (2 bit)
access : read-only

OC3FE : ADC_Channel 4 Result
bits : 2 - 2 (1 bit)
access : read-only

OC3PE : ADC_Channel 4 Result
bits : 3 - 3 (1 bit)
access : read-only

OC3M : ADC_Channel 4 Result
bits : 4 - 6 (3 bit)
access : read-only

OC3CE : ADC_Channel 4 Result
bits : 7 - 7 (1 bit)
access : read-only

CC4S : ADC_Channel 4 Result
bits : 8 - 9 (2 bit)
access : read-only

OC4FE : ADC_Channel 4 Result
bits : 10 - 10 (1 bit)
access : read-only

OC4PE : ADC_Channel 4 Result
bits : 11 - 11 (1 bit)
access : read-only

OC4M : ADC_Channel 4 Result
bits : 12 - 14 (3 bit)
access : read-only

OC4CE : ADC_Channel 4 Result
bits : 15 - 15 (1 bit)
access : read-only


CCER

TIM1 Captuer/Compare Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCER CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NE CC1NP CC2E CC2P CC2NE CC2NP CC3E CC3P CC3NE CC3NP CC4E CC4P

CC1E : ADC_Channel 5 Result
bits : 0 - 0 (1 bit)
access : read-write

CC1P : ADC_Channel 5 Result
bits : 1 - 1 (1 bit)
access : read-write

CC1NE : ADC_Channel 5 Result
bits : 2 - 2 (1 bit)
access : read-write

CC1NP : ADC_Channel 5 Result
bits : 3 - 3 (1 bit)
access : read-write

CC2E : ADC_Channel 5 Result
bits : 4 - 4 (1 bit)
access : read-write

CC2P : ADC_Channel 5 Result
bits : 5 - 5 (1 bit)
access : read-write

CC2NE : ADC_Channel 5 Result
bits : 6 - 6 (1 bit)
access : read-write

CC2NP : ADC_Channel 5 Result
bits : 7 - 7 (1 bit)
access : read-write

CC3E : ADC_Channel 5 Result
bits : 8 - 8 (1 bit)
access : read-write

CC3P : ADC_Channel 5 Result
bits : 9 - 9 (1 bit)
access : read-write

CC3NE : ADC_Channel 5 Result
bits : 10 - 10 (1 bit)
access : read-write

CC3NP : ADC_Channel 5 Result
bits : 11 - 11 (1 bit)
access : read-write

CC4E : ADC_Channel 5 Result
bits : 12 - 12 (1 bit)
access : read-write

CC4P : ADC_Channel 5 Result
bits : 13 - 13 (1 bit)
access : read-write


CNT

TIM1 Count
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : ADC_Channel 6 Result
bits : 0 - 15 (16 bit)
access : read-only


PSC

TIM1 Prescale Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : ADC_Channel 7 Result
bits : 0 - 15 (16 bit)
access : read-write


ARR

TIM1 Auto Load Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARR ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ADC_ Result
bits : 0 - 15 (16 bit)
access : read-write


RCR

TIM1 Repeate Count Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP

REP : ADC_Convect Result Compare High Therashold
bits : 0 - 7 (8 bit)
access : read-write


CCR1

Captuer/Compare Register1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : ADC Convect Result Compare High threshold
bits : 0 - 15 (16 bit)
access : read-write


CCR2

Capture/Compare Register2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2

CCR2 : ADC_Convect Result Compare Low Threshold
bits : 0 - 15 (16 bit)
access : read-only


CCR3

Capture/Compare Register3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR3 CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR3

CCR3 : ADC Channel 7~0 Interrupt Mask Config
bits : 0 - 15 (16 bit)
access : read-write


CR2

TIM1 Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCPC CCUS MMS TI1S OIS1 OIS1N OIS2 OIS2N OIS3 OIS3N OIS4

CCPC : ADC Convect Auto Triger 0
bits : 0 - 0 (1 bit)
access : read-write

CCUS : ADC Convect Auto Triger 1
bits : 2 - 2 (1 bit)
access : read-write

MMS : ADC_Convect mode Select
bits : 4 - 6 (3 bit)
access : read-write

TI1S : ADC_Convect Result Auto ADD
bits : 7 - 7 (1 bit)
access : read-write

OIS1 : ADC_Low threshold Compare Control
bits : 8 - 8 (1 bit)
access : read-write

OIS1N : ADC_High threshold Compare Control
bits : 9 - 9 (1 bit)
access : read-write

OIS2 : ADC_Area Compare Control
bits : 10 - 10 (1 bit)
access : read-write

OIS2N : ADC_Convect Result register Clear
bits : 11 - 11 (1 bit)
access : read-write

OIS3 : ADC_Convect Result register Clear
bits : 12 - 12 (1 bit)
access : read-write

OIS3N : ADC_Convect Result register Clear
bits : 13 - 13 (1 bit)
access : read-write

OIS4 : ADC_Convect Result register Clear
bits : 14 - 14 (1 bit)
access : read-write


CCR4

TIM1 Capture/Compare Register4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR4 CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR4

CCR4 : Reload value to use for 10ms timing
bits : 0 - 15 (16 bit)
access : read-write


BDTR

TIM1 Brush and DEAD Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTR BDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTG LOCK OSSI OSSR BKE BKP AOE MOE

DTG : Reload value to use for 10ms timing
bits : 0 - 7 (8 bit)
access : read-write

LOCK : LLT
bits : 8 - 9 (2 bit)
access : read-write

OSSI : HHT
bits : 10 - 10 (1 bit)
access : read-write

OSSR : REG
bits : 11 - 11 (1 bit)
access : read-write

BKE : CON
bits : 12 - 12 (1 bit)
access : read-write

BKP : CON
bits : 13 - 13 (1 bit)
access : read-write

AOE : CON
bits : 14 - 14 (1 bit)
access : read-write

MOE : CON
bits : 15 - 15 (1 bit)
access : read-write


SMCR

TIM1 Slave mode Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMCR SMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS TS MSM ETF ETPS ECE ETP

SMS : ADC Continue Convect Channel 7-0 Enable
bits : 0 - 2 (3 bit)
access : read-write

TS : ADC Continue Convect Times Config
bits : 4 - 6 (3 bit)
access : read-write

MSM : ADC Convect Rounte Mode Select
bits : 7 - 7 (1 bit)
access : read-write

ETF : ADC Convect Rounte Mode Select
bits : 8 - 11 (4 bit)
access : read-write

ETPS : ADC Convect Rounte Mode Select
bits : 12 - 13 (2 bit)
access : read-write

ECE : ADC Convect Rounte Mode Select
bits : 14 - 14 (1 bit)
access : read-write

ETP : ADC Convect Rounte Mode Select
bits : 15 - 15 (1 bit)
access : read-write


DIER

TIM1 Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIER DIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE CC2IE CC3IE CC4IE COMIE TIE BIE

UIE : ADC Channel 0 Result
bits : 0 - 0 (1 bit)
access : read-write

CC1IE : ADC Channel 0 Result
bits : 1 - 1 (1 bit)
access : read-write

CC2IE : ADC Channel 0 Result
bits : 2 - 2 (1 bit)
access : read-write

CC3IE : ADC Channel 0 Result
bits : 3 - 3 (1 bit)
access : read-write

CC4IE : ADC Channel 0 Result
bits : 4 - 4 (1 bit)
access : read-write

COMIE : ADC Channel 0 Result
bits : 5 - 5 (1 bit)
access : read-write

TIE : ADC Channel 0 Result
bits : 6 - 6 (1 bit)
access : read-write

BIE : ADC Channel 0 Result
bits : 7 - 7 (1 bit)
access : read-write



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