\n

GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection :

Registers

DIRCR

INTEN

RAWINTST

MSKINTSR

INTCLR

INTTYPCR

INTPOLCR

INTANY

ODSET

ODCLR

INDBEN

DBCLKCR

PUPDR

OTYPER

SLEWCR

DRVCR

AFR

ODR

IDR


DIRCR

Input Output model Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIRCR DIRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxDIR0 PxDIR1 PxDIR2 PxDIR3 PxDIR4 PxDIR5 PxDIR6 PxDIR7

PxDIR0 : PA DIR0
bits : 0 - 0 (1 bit)
access : read-write

PxDIR1 : PA DIR1
bits : 1 - 1 (1 bit)
access : read-write

PxDIR2 : PA DIR2
bits : 2 - 2 (1 bit)
access : read-write

PxDIR3 : PA DIR3
bits : 3 - 3 (1 bit)
access : read-write

PxDIR4 : PA DIR4
bits : 4 - 4 (1 bit)
access : read-write

PxDIR5 : PA DIR5
bits : 5 - 5 (1 bit)
access : read-write

PxDIR6 : PA DIR6
bits : 6 - 6 (1 bit)
access : read-write

PxDIR7 : PA DIR7
bits : 7 - 7 (1 bit)
access : read-write


INTEN

Inerrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxIEN0 PxIEN1 PxIEN2 PxIEN3 PxIEN4 PxIEN5 PxIEN6 PxIEN7

PxIEN0 : PA Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

PxIEN1 : PA Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

PxIEN2 : PA Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

PxIEN3 : PA Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

PxIEN4 : PA Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

PxIEN5 : PA Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

PxIEN6 : PA Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

PxIEN7 : PA Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write


RAWINTST

Interrupt Raw Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAWINTST RAWINTST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxRIS0 PxRIS1 PxRIS2 PxRIS3 PxRIS4 PxRIS5 PxRIS6 PxRIS7

PxRIS0 : PA RIS
bits : 0 - 0 (1 bit)
access : read-only

PxRIS1 : PA RIS
bits : 1 - 1 (1 bit)
access : read-only

PxRIS2 : PA RIS
bits : 2 - 2 (1 bit)
access : read-only

PxRIS3 : PA RIS
bits : 3 - 3 (1 bit)
access : read-only

PxRIS4 : PA RIS
bits : 4 - 4 (1 bit)
access : read-only

PxRIS5 : PA RIS
bits : 5 - 5 (1 bit)
access : read-only

PxRIS6 : PA RIS
bits : 6 - 6 (1 bit)
access : read-only

PxRIS7 : PA RIS
bits : 7 - 7 (1 bit)
access : read-only


MSKINTSR

Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSKINTSR MSKINTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxMIS0 PxMIS1 PxMIS2 PxMIS3 PxMIS4 PxMIS5 PxMIS6 PxMIS7

PxMIS0 : PA MIS0
bits : 0 - 0 (1 bit)
access : read-only

PxMIS1 : PA MIS1
bits : 1 - 1 (1 bit)
access : read-only

PxMIS2 : PA MIS2
bits : 2 - 2 (1 bit)
access : read-only

PxMIS3 : PA MIS
bits : 3 - 3 (1 bit)
access : read-only

PxMIS4 : PA MIS
bits : 4 - 4 (1 bit)
access : read-only

PxMIS5 : PA MIS
bits : 5 - 5 (1 bit)
access : read-only

PxMIS6 : PA MIS
bits : 6 - 6 (1 bit)
access : read-only

PxMIS7 : PA MIS
bits : 7 - 7 (1 bit)
access : read-only


INTCLR

Interrupt Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTCLR INTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxICLR0 PxICLR1 PxICLR2 PxICLR3 PxICLR4 PxICLR5 PxICLR6 PxICLR7

PxICLR0 : PA ICLR0
bits : 0 - 0 (1 bit)
access : write-only

PxICLR1 : PA ICLR
bits : 1 - 1 (1 bit)
access : write-only

PxICLR2 : PA ICLR
bits : 2 - 2 (1 bit)
access : write-only

PxICLR3 : PA ICLR
bits : 3 - 3 (1 bit)
access : write-only

PxICLR4 : PA ICLR
bits : 4 - 4 (1 bit)
access : write-only

PxICLR5 : PA ICLR
bits : 5 - 5 (1 bit)
access : write-only

PxICLR6 : PA ICLR
bits : 6 - 6 (1 bit)
access : write-only

PxICLR7 : PA ICLR
bits : 7 - 7 (1 bit)
access : write-only


INTTYPCR

Interrupt Style Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTTYPCR INTTYPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxITYPE0 PxITYPE1 PxITYPE2 PxITYPE3 PxITYPE4 PxITYPE5 PxITYPE6 PxITYPE7

PxITYPE0 : PA Interrupt type
bits : 0 - 0 (1 bit)
access : read-write

PxITYPE1 : PA Interrupt type
bits : 1 - 1 (1 bit)
access : read-write

PxITYPE2 : PA Interrupt type
bits : 2 - 2 (1 bit)
access : read-write

PxITYPE3 : PA Interrupt type
bits : 3 - 3 (1 bit)
access : read-write

PxITYPE4 : PA Interrupt type
bits : 4 - 4 (1 bit)
access : read-write

PxITYPE5 : PA Interrupt type
bits : 5 - 5 (1 bit)
access : read-write

PxITYPE6 : PA Interrupt type
bits : 6 - 6 (1 bit)
access : read-write

PxITYPE7 : PA Interrupt type
bits : 7 - 7 (1 bit)
access : read-write


INTPOLCR

Interrupt Sytle Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTPOLCR INTPOLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxIVAL0 PxIVAL1 PxIVAL2 PxIVAL3 PxIVAL4 PxIVAL5 PxIVAL6 PxIVAL7

PxIVAL0 : PA Interrupt Value
bits : 0 - 0 (1 bit)
access : read-write

PxIVAL1 : PA Interrupt Value
bits : 1 - 1 (1 bit)
access : read-write

PxIVAL2 : PA Interrupt Value
bits : 2 - 2 (1 bit)
access : read-write

PxIVAL3 : PA Interrupt Value
bits : 3 - 3 (1 bit)
access : read-write

PxIVAL4 : PA Interrupt Value
bits : 4 - 4 (1 bit)
access : read-write

PxIVAL5 : PA Interrupt Value
bits : 5 - 5 (1 bit)
access : read-write

PxIVAL6 : PA Interrupt Value
bits : 6 - 6 (1 bit)
access : read-write

PxIVAL7 : PA Interrupt Value
bits : 7 - 7 (1 bit)
access : read-write


INTANY

Edge Trigger Interrupt Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTANY INTANY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxIANY0 PxIANY1 PxIANY2 PxIANY3 PxIANY4 PxIANY5 PxIANY6 PxIANY7

PxIANY0 : PA IANY
bits : 0 - 0 (1 bit)
access : read-write

PxIANY1 : PA IANY
bits : 1 - 1 (1 bit)
access : read-write

PxIANY2 : PA IANY
bits : 2 - 2 (1 bit)
access : read-write

PxIANY3 : PA IANY
bits : 3 - 3 (1 bit)
access : read-write

PxIANY4 : PA IANY
bits : 4 - 4 (1 bit)
access : read-write

PxIANY5 : PA IANY
bits : 5 - 5 (1 bit)
access : read-write

PxIANY6 : PA IANY
bits : 6 - 6 (1 bit)
access : read-write

PxIANY7 : PA IANY
bits : 7 - 7 (1 bit)
access : read-write


ODSET

Output Setting Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODSET ODSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxODSET0 PxODSET1 PxODSET2 PxODSET3 PxODSET4 PxODSET5 PxODSET6 PxODSET7

PxODSET0 : PA Output Setting bit
bits : 0 - 0 (1 bit)
access : write-only

PxODSET1 : PA Output Setting bit
bits : 1 - 1 (1 bit)
access : write-only

PxODSET2 : PA Output Setting bit
bits : 2 - 2 (1 bit)
access : write-only

PxODSET3 : PA Output Setting bit
bits : 3 - 3 (1 bit)
access : write-only

PxODSET4 : PA Output Setting bit
bits : 4 - 4 (1 bit)
access : write-only

PxODSET5 : PA Output Setting bit
bits : 5 - 5 (1 bit)
access : write-only

PxODSET6 : PA Output Setting bit
bits : 6 - 6 (1 bit)
access : write-only

PxODSET7 : PA Output Setting bit
bits : 7 - 7 (1 bit)
access : write-only


ODCLR

Output Clear Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODCLR ODCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxODCLR0 PxODCLR1 PxODCLR2 PxODCLR3 PxODCLR4 PxODCLR5 PxODCLR6 PxODCLR7

PxODCLR0 : PAODCLR
bits : 0 - 0 (1 bit)
access : write-only

PxODCLR1 : PAODCLR
bits : 1 - 1 (1 bit)
access : write-only

PxODCLR2 : PAODCLR
bits : 2 - 2 (1 bit)
access : write-only

PxODCLR3 : PAODCLR
bits : 3 - 3 (1 bit)
access : write-only

PxODCLR4 : PAODCLR
bits : 4 - 4 (1 bit)
access : write-only

PxODCLR5 : PAODCLR
bits : 5 - 5 (1 bit)
access : write-only

PxODCLR6 : PAODCLR
bits : 6 - 6 (1 bit)
access : write-only

PxODCLR7 : PAODCLR
bits : 7 - 7 (1 bit)
access : write-only


INDBEN

Input Debounce and synchronous Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INDBEN INDBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxDIDB SYNC_EN

PxDIDB : Reload value to use for 10ms timing
bits : 0 - 7 (8 bit)
access : read-write

SYNC_EN : enable
bits : 8 - 8 (1 bit)
access : read-write


DBCLKCR

Input Debounce clock Config register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLKCR DBCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBCLK_DIV DBCLKEN

DBCLK_DIV : DB CLK
bits : 0 - 3 (4 bit)
access : read-write

DBCLKEN : DB
bits : 4 - 4 (1 bit)
access : read-write


PUPDR

PullUp and PullDown Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUPDR PUPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxPUPD0 PxPUPD1 PxPUPD2 PxPUPD3 PxPUPD4 PxPUPD5 PxPUPD6 PxPUPD7

PxPUPD0 : PA PullUP PullDown
bits : 0 - 1 (2 bit)
access : read-write

PxPUPD1 : PA PullUP PullDown
bits : 2 - 3 (2 bit)
access : read-write

PxPUPD2 : PA PullUP PullDown
bits : 4 - 5 (2 bit)
access : read-write

PxPUPD3 : PA PullUP PullDown
bits : 6 - 7 (2 bit)
access : read-write

PxPUPD4 : PA PullUP PullDown
bits : 8 - 9 (2 bit)
access : read-write

PxPUPD5 : PA PullUP PullDown
bits : 10 - 11 (2 bit)
access : read-write

PxPUPD6 : PA PullUP PullDown
bits : 12 - 13 (2 bit)
access : read-write

PxPUPD7 : PA PullUP PullDown
bits : 14 - 15 (2 bit)
access : read-write


OTYPER

Output Type register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTYPER OTYPER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxOTYP0 PxOTYP1 PxOTYP2 PxOTYP3 PxOTYP4 PxOTYP5 PxOTYP6 PxOTYP7

PxOTYP0 : PA Output Type0
bits : 0 - 0 (1 bit)
access : read-write

PxOTYP1 : PA Output Type1
bits : 1 - 1 (1 bit)
access : read-write

PxOTYP2 : PA Output Type2
bits : 2 - 2 (1 bit)
access : read-write

PxOTYP3 : PA Output Type3
bits : 3 - 3 (1 bit)
access : read-write

PxOTYP4 : PA Output Type4
bits : 4 - 4 (1 bit)
access : read-write

PxOTYP5 : PA Output Type5
bits : 5 - 5 (1 bit)
access : read-write

PxOTYP6 : PA Output Type6
bits : 6 - 6 (1 bit)
access : read-write

PxOTYP7 : PA Output Type7
bits : 7 - 7 (1 bit)
access : read-write


SLEWCR

Voltage Convertion Speed Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEWCR SLEWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASR0 PxSR1 PxSR2 PxSR3 PxSR4 PxSR5 PxSR6 PxSR7

PASR0 : PA
bits : 0 - 0 (1 bit)
access : read-write

PxSR1 : PA
bits : 1 - 1 (1 bit)
access : read-write

PxSR2 : PA
bits : 2 - 2 (1 bit)
access : read-write

PxSR3 : PA
bits : 3 - 3 (1 bit)
access : read-write

PxSR4 : PA
bits : 4 - 4 (1 bit)
access : read-write

PxSR5 : PA
bits : 5 - 5 (1 bit)
access : read-write

PxSR6 : PA
bits : 6 - 6 (1 bit)
access : read-write

PxSR7 : PA
bits : 7 - 7 (1 bit)
access : read-write


DRVCR

Driver Strength Config
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRVCR DRVCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxDRV0 PxDRV1 PxDRV2 PxDRV3 PxDRV4 PxDRV5 PxDRV6 PxDRV7

PxDRV0 : PADRV
bits : 0 - 0 (1 bit)
access : read-write

PxDRV1 : PADRV
bits : 1 - 1 (1 bit)
access : read-write

PxDRV2 : PADRV
bits : 2 - 2 (1 bit)
access : read-write

PxDRV3 : PADRV
bits : 3 - 3 (1 bit)
access : read-write

PxDRV4 : PADRV
bits : 4 - 4 (1 bit)
access : read-write

PxDRV5 : PADRV
bits : 5 - 5 (1 bit)
access : read-write

PxDRV6 : PADRV
bits : 6 - 6 (1 bit)
access : read-write

PxDRV7 : PADRV
bits : 7 - 7 (1 bit)
access : read-write


AFR

Multiplex Function Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFR AFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxAFR0 PxAFR1 PxAFR2 PxAFR3 PxAFR4 PxAFR5 PxAFR6 PxAFR7

PxAFR0 : PA AFR
bits : 0 - 3 (4 bit)
access : read-write

PxAFR1 : PA AFR
bits : 4 - 7 (4 bit)
access : read-write

PxAFR2 : PA AFR
bits : 8 - 11 (4 bit)
access : read-write

PxAFR3 : PA AFR
bits : 12 - 15 (4 bit)
access : read-write

PxAFR4 : PA AFR
bits : 16 - 19 (4 bit)
access : read-write

PxAFR5 : PA AFR
bits : 20 - 23 (4 bit)
access : read-write

PxAFR6 : PA AFR
bits : 24 - 27 (4 bit)
access : read-write

PxAFR7 : PA AFR
bits : 28 - 31 (4 bit)
access : read-write


ODR

Output Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ODR ODR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxOD0 PxOD1 PxOD2 PxOD3 PxOD4 PxOD5 PxOD6 PxOD7

PxOD0 : PA Output Value Config
bits : 0 - 0 (1 bit)
access : read-write

PxOD1 : PA Output Value Config
bits : 1 - 1 (1 bit)
access : read-write

PxOD2 : PA Output Value Config
bits : 2 - 2 (1 bit)
access : read-write

PxOD3 : PA Output Value Config
bits : 3 - 3 (1 bit)
access : read-write

PxOD4 : PA Output Value Config
bits : 4 - 4 (1 bit)
access : read-write

PxOD5 : PA Output Value Config
bits : 5 - 5 (1 bit)
access : read-write

PxOD6 : PA Output Value Config
bits : 6 - 6 (1 bit)
access : read-write

PxOD7 : PA Output Value Config
bits : 7 - 7 (1 bit)
access : read-write


IDR

Input Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDR IDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PxID0 PxID1 PxID2 PxID3 PxID4 PxID5 PxID6 PxID7

PxID0 : PA Input Value
bits : 0 - 0 (1 bit)
access : read-write

PxID1 : PA Input Value
bits : 1 - 1 (1 bit)
access : read-write

PxID2 : PA Input Value
bits : 2 - 2 (1 bit)
access : read-write

PxID3 : PA Input Value
bits : 3 - 3 (1 bit)
access : read-write

PxID4 : PA Input Value
bits : 4 - 4 (1 bit)
access : read-write

PxID5 : PA Input Value
bits : 5 - 5 (1 bit)
access : read-write

PxID6 : PA Input Value
bits : 6 - 6 (1 bit)
access : read-write

PxID7 : PA Input Value
bits : 7 - 7 (1 bit)
access : read-write



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