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SYSCON

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection :

Registers

CFGR0

TIM1CR

TIM2CR

PORTINTCR

UNLOCK

PORTCR

PCACR


CFGR0

System Control setting regist 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR0 CFGR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKUPEN DBGDLSP_DIS KEY

LOCKUPEN : LOCKUP
bits : 0 - 0 (1 bit)
access : read-write

DBGDLSP_DIS : Allow Debug Enter DeepSleep Mode
bits : 1 - 1 (1 bit)
access : read-write

KEY : KEY
bits : 16 - 31 (16 bit)
access : read-write


TIM1CR

TIM1 Channel Source Select
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM1CR TIM1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1CH1IN_SEL TIM1CH2IN_SEL TIM1CH3IN_SEL TIM1CH4IN_SEL TIM1ETR_SEL TIM1BRKOUTCFG DSLPBRKEN CLKFAILBRKEN

TIM1CH1IN_SEL : Source
bits : 0 - 2 (3 bit)
access : read-write

TIM1CH2IN_SEL : Source
bits : 4 - 6 (3 bit)
access : read-write

TIM1CH3IN_SEL : Channel
bits : 8 - 10 (3 bit)
access : read-write

TIM1CH4IN_SEL : Channel
bits : 12 - 14 (3 bit)
access : read-write

TIM1ETR_SEL : Channel
bits : 16 - 19 (4 bit)
access : read-write

TIM1BRKOUTCFG : Channel
bits : 20 - 20 (1 bit)
access : read-write

DSLPBRKEN : Channel
bits : 21 - 21 (1 bit)
access : read-write

CLKFAILBRKEN : Channel
bits : 22 - 22 (1 bit)
access : read-write


TIM2CR

TIM2 Channel Source Select
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIM2CR TIM2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2CH1IN_SEL TIM2CH2IN_SEL TIM2CH3IN_SEL TIM2CH4IN_SEL TIM2ETR_SEL

TIM2CH1IN_SEL : Source
bits : 0 - 2 (3 bit)
access : read-write

TIM2CH2IN_SEL : Channel
bits : 4 - 6 (3 bit)
access : read-write

TIM2CH3IN_SEL : SOURCE
bits : 8 - 10 (3 bit)
access : read-write

TIM2CH4IN_SEL : SOURCE
bits : 12 - 14 (3 bit)
access : read-write

TIM2ETR_SEL : SOURCE
bits : 16 - 19 (4 bit)
access : read-write


PORTINTCR

PORT INTERRUPT MODE SETTING
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORTINTCR PORTINTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADINTSEL PADDLSPCON KEY

PADINTSEL : Endpoint Interrupt Mode Select
bits : 0 - 0 (1 bit)
access : read-write

PADDLSPCON : PADDLSP
bits : 1 - 1 (1 bit)
access : read-write

KEY : KEY
bits : 16 - 31 (16 bit)
access : write-only


UNLOCK

Syscon Register Write Enable
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNLOCK UNLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNLOCK KEY

UNLOCK : read_write
bits : 0 - 0 (1 bit)
access : read-only

KEY : KEY
bits : 1 - 31 (31 bit)
access : write-only


PORTCR

PORT control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORTCR PORTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPINCS_SEL TIM10_GATE_SEL TIM11_GATE_SEL LPTIM_GATE_SEL

SPINCS_SEL : SLAVE
bits : 0 - 3 (4 bit)
access : read-write

TIM10_GATE_SEL : TIMER10 GATE
bits : 4 - 5 (2 bit)
access : read-write

TIM11_GATE_SEL : TIMER11 GATE
bits : 6 - 7 (2 bit)
access : read-write

LPTIM_GATE_SEL : LPTIM GATE
bits : 8 - 9 (2 bit)
access : read-write


PCACR

PCA Capture channel source select
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCACR PCACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCA_CAP0_SEL PCA_CAP1_SEL PCA_CAP2_SEL PCA_CAP3_SEL PCA_CAP4_SEL

PCA_CAP0_SEL : PAC Channel
bits : 0 - 1 (2 bit)
access : read-write

PCA_CAP1_SEL : PAC
bits : 2 - 3 (2 bit)
access : read-write

PCA_CAP2_SEL : PCA_CHANNEL
bits : 4 - 5 (2 bit)
access : read-write

PCA_CAP3_SEL : PCA_CHANNEL
bits : 6 - 7 (2 bit)
access : read-write

PCA_CAP4_SEL : PCA_CHANNEL
bits : 8 - 9 (2 bit)
access : read-write



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