\n

RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection :

Registers

HCLKDIV

MCOCR

RSTCR

RSTSR

SYSCLKCR

SYSCLKSEL

HIRCCR

HXTCR

LIRCCR

LXTCR

IRQLATENCY

STICKCR

PCLKDIV

SWDIOCR

PERIRST

RTCRST

UNLOCK

HCLKEN

PCLKEN


HCLKDIV

AHB CLK Prescale
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCLKDIV HCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBCKDIV

AHBCKDIV : System HCLK Prescale
bits : 0 - 7 (8 bit)
access : read-write


MCOCR

Clock Output Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCOCR MCOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCODIV MCOSEL MCOEN

MCODIV : FCLK Prescale
bits : 0 - 7 (8 bit)
access : read-write

MCOSEL : Clock Output Source Select
bits : 8 - 10 (3 bit)
access : read-write

MCOEN : MCO Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.


RSTCR

System Reset Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCR RSTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCURST CPURST RSTKEY

MCURST : RESET
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : 0

Normal

1 : 1

Reset MCU

End of enumeration elements list.

CPURST : CUP Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : 0

Normal

1 : 1

Reset CPU

End of enumeration elements list.

RSTKEY : KEY
bits : 2 - 31 (30 bit)
access : read-write


RSTSR

Reset Status
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSR RSTSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCURST CPURST WWDGRST IWDGRST LVDRST PORRST LOCKUPRST PADRST SFTRST

MCURST : MCU Reset Flag
bits : 0 - 0 (1 bit)
access : read-write

CPURST : CPU reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : 0

No CPU Reset Happen

1 : 1

CPU Reset Happen

End of enumeration elements list.

WWDGRST : WWDG RST FLAG
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : 0

No WWDG RST

1 : 1

WWDG RST

End of enumeration elements list.

IWDGRST : IWDG RST FLAG
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : 0

No IWDG RST HAPPEN

1 : 1

WWDG RST HAPPEN

End of enumeration elements list.

LVDRST : LVD RST FLAG
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : 0

NO LVD RST

1 : 1

LVD RST

End of enumeration elements list.

PORRST : POR RST FLAG
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : 0

NO VCore POR RST

1 : 1

VCore POR RST

End of enumeration elements list.

LOCKUPRST : LOCKUP RST FLAG
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : 0

NO LOCKUP RST

1 : 1

LOCKUP RST

End of enumeration elements list.

PADRST : PAD RST FLAG
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : 0

NO PAD RST

1 : 1

PAD RST

End of enumeration elements list.

SFTRST : Software RST FLAG
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : 0

NO SFT RST

1 : 1

SFT RST

End of enumeration elements list.


SYSCLKCR

CLK Setting
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCLKCR SYSCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRCEN HXTEN LIRCEN HXTBYP HXTPORT CLKFAILEN WKBYHIRC KEY

HIRCEN : HIRC Enable
bits : 0 - 0 (1 bit)
access : read-write

HXTEN : HXT Enable
bits : 1 - 1 (1 bit)
access : read-write

LIRCEN : LIRC Enable
bits : 2 - 2 (1 bit)
access : read-write

HXTBYP : HXT Bypass
bits : 5 - 5 (1 bit)
access : read-write

HXTPORT : HXT Port Function Config
bits : 6 - 6 (1 bit)
access : read-write

CLKFAILEN : CLK FAIL Enable
bits : 8 - 8 (1 bit)
access : read-write

WKBYHIRC : XX
bits : 15 - 15 (1 bit)
access : read-write

KEY : KEY
bits : 16 - 31 (16 bit)
access : write-only


SYSCLKSEL

System Clock Select
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCLKSEL SYSCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSW KEY

CLKSW : System Clock Source Select
bits : 0 - 3 (4 bit)
access : read-write

KEY : KEY
bits : 16 - 31 (16 bit)
access : write-only


HIRCCR

HIRC Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIRCCR HIRCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRCTRIM HIRCRDY KEY

HIRCTRIM : HIRCTRIM
bits : 0 - 11 (12 bit)
access : read-write

HIRCRDY : HIRC RDY
bits : 12 - 12 (1 bit)
access : read-only

KEY : KEY
bits : 16 - 31 (16 bit)
access : write-only


HXTCR

HXT Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HXTCR HXTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTDRV HXTSTARTUP HXTRDY

HXTDRV : DRV
bits : 0 - 2 (3 bit)
access : read-write

HXTSTARTUP : TIME
bits : 4 - 5 (2 bit)
access : read-write

HXTRDY : HXT Ready
bits : 6 - 6 (1 bit)
access : read-write


LIRCCR

LIRC Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIRCCR LIRCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIRCTRIM LIRCSTARTUP LIRCRDY KEY

LIRCTRIM : TRIM
bits : 0 - 8 (9 bit)
access : read-write

LIRCSTARTUP : TIME
bits : 10 - 11 (2 bit)
access : read-write

LIRCRDY : FLG
bits : 12 - 12 (1 bit)
access : read-only

KEY : KEY
bits : 16 - 31 (16 bit)
access : write-only


LXTCR

LXT Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LXTCR LXTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXTDRV LXTSTARTUP LXTRDY LXTEN LXTBYP LXTAON LXTPORT KEY

LXTDRV : DRV
bits : 0 - 3 (4 bit)
access : read-write

LXTSTARTUP : TIMER
bits : 4 - 5 (2 bit)
access : read-write

LXTRDY : RDY
bits : 6 - 6 (1 bit)
access : read-write

LXTEN : EN
bits : 8 - 8 (1 bit)
access : read-write

LXTBYP : BYP
bits : 9 - 9 (1 bit)
access : read-write

LXTAON : ON
bits : 10 - 10 (1 bit)
access : read-write

LXTPORT : PORT
bits : 11 - 11 (1 bit)
access : read-write

KEY : KEY
bits : 16 - 31 (16 bit)
access : write-only


IRQLATENCY

M0 IRQ Delay
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQLATENCY IRQLATENCY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQLATENCY

IRQLATENCY : IRQ
bits : 0 - 7 (8 bit)
access : read-write


STICKCR

SysTick Timer Circle Adjust
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STICKCR STICKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCALIB SKEW NOREF

STCALIB : Systick
bits : 0 - 23 (24 bit)
access : read-write

SKEW : Clock Skew
bits : 24 - 24 (1 bit)
access : read-write

NOREF : No Ref
bits : 25 - 25 (1 bit)
access : read-write


PCLKDIV

APB CLK Prescale
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLKDIV PCLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APBCKDIV

APBCKDIV : System PCLK Prescale
bits : 0 - 7 (8 bit)
access : read-write


SWDIOCR

Endpoint Function Select
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWDIOCR SWDIOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWDPORT KEY

SWDPORT : PORT
bits : 0 - 0 (1 bit)
access : read-write

KEY : KEY
bits : 16 - 31 (16 bit)
access : write-only


PERIRST

Peripheral Model Control
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIRST PERIRST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0RST UART1RST I2CRST LPUARTRST SPIRST LPTIMRST BASETIMRST SYSCONRST PCARST OWIRERST TIM1RST TIM2RST WWDGRST ADCRST AWKRST CLKTRIMRST LVDVCRST BEEPRST DBGRST GPIOARST GPIOBRST GPIOCRST GPIODRST CRCRST

UART0RST : RST
bits : 0 - 0 (1 bit)
access : read-write

UART1RST : RST
bits : 1 - 1 (1 bit)
access : read-write

I2CRST : RST
bits : 2 - 2 (1 bit)
access : read-write

LPUARTRST : RST
bits : 3 - 3 (1 bit)
access : read-write

SPIRST : RST
bits : 4 - 4 (1 bit)
access : read-write

LPTIMRST : RST
bits : 5 - 5 (1 bit)
access : read-write

BASETIMRST : RST
bits : 6 - 6 (1 bit)
access : read-write

SYSCONRST : RST
bits : 7 - 7 (1 bit)
access : read-write

PCARST : RST
bits : 8 - 8 (1 bit)
access : read-write

OWIRERST : RST
bits : 9 - 9 (1 bit)
access : read-write

TIM1RST : RST
bits : 10 - 10 (1 bit)
access : read-write

TIM2RST : RST
bits : 11 - 11 (1 bit)
access : read-write

WWDGRST : RST
bits : 12 - 12 (1 bit)
access : read-write

ADCRST : RST
bits : 13 - 13 (1 bit)
access : read-write

AWKRST : RST
bits : 14 - 14 (1 bit)
access : read-write

CLKTRIMRST : RST
bits : 16 - 16 (1 bit)
access : read-write

LVDVCRST : RST
bits : 18 - 18 (1 bit)
access : read-write

BEEPRST : RST
bits : 19 - 19 (1 bit)
access : read-write

DBGRST : RST
bits : 20 - 20 (1 bit)
access : read-write

GPIOARST : RST
bits : 24 - 24 (1 bit)
access : read-write

GPIOBRST : RST
bits : 25 - 25 (1 bit)
access : read-write

GPIOCRST : RST
bits : 26 - 26 (1 bit)
access : read-write

GPIODRST : RST
bits : 27 - 27 (1 bit)
access : read-write

CRCRST : RST
bits : 28 - 28 (1 bit)
access : read-write


RTCRST

RTC Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCRST RTCRST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTCRST KEY

RTCRST : RTC RST
bits : 0 - 0 (1 bit)
access : read-write

KEY : KEY
bits : 16 - 31 (16 bit)
access : write-only


UNLOCK

Register Protect
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNLOCK UNLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UNLOCK KEY

UNLOCK : UNLOCK
bits : 0 - 0 (1 bit)
access : read-write

KEY : KEY
bits : 1 - 31 (31 bit)
access : write-only


HCLKEN

AHB Peripheral Model Clk Enable
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCLKEN HCLKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOACKEN GPIOBCKEN GPIOCCKEN GPIODCKEN CRCCKEN FLASHCKEN

GPIOACKEN : GPIOA CLK Enable
bits : 0 - 0 (1 bit)
access : read-write

GPIOBCKEN : GPIOB CLK Enable
bits : 1 - 1 (1 bit)
access : read-write

GPIOCCKEN : GPIOC CLK Enable
bits : 2 - 2 (1 bit)
access : read-write

GPIODCKEN : GPIOD CLK Enable
bits : 3 - 3 (1 bit)
access : read-write

CRCCKEN : CRC CLK Enable
bits : 4 - 4 (1 bit)
access : read-write

FLASHCKEN : Flash CLK Enable
bits : 8 - 8 (1 bit)
access : read-write


PCLKEN

APB Peripheral Model CLK Enable
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLKEN PCLKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0CKEN UART1CKEN I2CCKEN LPUARTCKEN SPICKEN LPTIMCKEN BASETIMCKEN SYSCONCKEN PCACKEN OWIRECKEN TIM1CKEN TIM2CKEN WWDGCKEN ADCCKEN AWKCKEN RTCCKEN CLKCTRIMCKEN IWDGCKEN LVDVCCKEN BEEPCKEN DBGCKEN

UART0CKEN : UART0 CLK Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

UART1CKEN : UART1 CLK Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

I2CCKEN : I2C CK Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

LPUARTCKEN : LPUART CLK Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

SPICKEN : SPI CLK Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

LPTIMCKEN : LPTIMCKEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

BASETIMCKEN : BASE timer clk enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

SYSCONCKEN : System Control CLK Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

PCACKEN : PCA Clk Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

OWIRECKEN : 1-WIRE Clk Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

TIM1CKEN : TIM1 Clk Enable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

TIM2CKEN : TIM2 Clk Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

WWDGCKEN : WWDG Clk Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

ADCCKEN : ADC Clk Enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

AWKCKEN : ADC Clk Enable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

RTCCKEN : RTC Clk Enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

CLKCTRIMCKEN : CLKTRIM CLK Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

IWDGCKEN : IWDG CLK Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

LVDVCCKEN : LVD VC CLK Enable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

BEEPCKEN : BEEP CLK Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.

DBGCKEN : DBG CLK Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : 0

Disable

1 : 1

Enable

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.