Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
CKGEN Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCLK_SEL : system clock select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Internal RC
#1 : 01
PLL Output
#10 : 10
External XOSC
End of enumeration elements list.
SYSCLK_DIV : System Clcok Divider
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
System Clock Divided By 1
#01 : 01
System Clock Divided By 2
#10 : 10
System Clock Divided By 3
#11 : 11
System Clock Divided By 4
End of enumeration elements list.
APBCLK_DIV : APB Clcok Divider
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
APB Clock Divided By 1
#01 : 01
APB Clock Divided By 2
#10 : 10
APB Clock Divided By 3
#11 : 11
APB Clock Divided By 4
End of enumeration elements list.
XOSC_MON_EN : XOSC Monitor Function Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Monitor Function Disable
#1 : 1
Monitor Function Enable
End of enumeration elements list.
PLL_REF_SEL : PLL Reference Clock Select
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal RC
#1 : 1
External XOSC
End of enumeration elements list.
CAN0_TIMCLK_DIV : CAN0 Clock Divider
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 00
CAN0 Clock Divided By 8
#01 : 01
CAN0 Clock Divided By 16
#10 : 10
CAN0 Clock Divided By 24
#11 : 11
CAN0 Clock Divided By 48
End of enumeration elements list.
CAN0_CLK_SEL : CAN0 Clock Source Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
External XOSC Clock
#1 : 1
AHB Clock Divided
End of enumeration elements list.
MCU Reset Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POR_RESET_STATUS : POR Reset Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
LVD_RESET_STATUS : LVD Reset Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
EXT_RESET_STATUS : EXT Reset Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
WDT_RESET_STATUS : WDT Reset Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
WDT_32K_RESET_STATUS : WDT 32K Reset Flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
CPU_SYSRESET_STATUS : CPU Sysreset Reset Flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
CPU_LOCKUP_RST_STATUS : CPU Lockup Reset Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
PLL_UNLOCK_RST_STATUS : PLL Unlock Reset Flag
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
XOSC_LOSS_STATUS : XOSC Loss Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset Not Happen
#1 : 1
Reset Happen
End of enumeration elements list.
CLR_RESET_STATUS : clear All Reset Status
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
reset update
#1 : 1
clear all reset status
End of enumeration elements list.
Periph Software Reset Control 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRST_UART0 : UART0 Software Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Active
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_UART1 : UART1 Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Active
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_UART2 : UART2 Software Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_SPI0 : SPI0 Software Reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_SPI1 : SPI1 Software Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_I2C0 : I2C0 Software Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_I2C1 : I2C1 Software Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_PWDT0 : PWDT0 Software Reset
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_PWM0 : PWM0 Software Reset
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_PWM1 : PWM1 Software Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_TIMER : TIMER Software Reset
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_RTC : RTC Software Reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_DMA0 : DMA0 Software Reset
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_GPIO : GPIO Software Reset
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_WDG : WDG Software Reset
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_CRC : CRC Software Reset
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_CAN0 : CAN0 Software Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
Periph Software Reset Control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRST_CTU : CTU Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Active
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_ADC0 : ADC0 Software Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_ACMP0 : ACMP0 Software Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_ANA_REG : Analog Register Software Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
SRST_PWDT1 : PWDT1 Software Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset Actsive
#1 : 1
Reset Inactive
End of enumeration elements list.
Periph Clock Enable Control 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART0_EN : UART0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
UART1_EN : UART1 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
UART2_EN : UART2 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
SPI1_EN : SPI1 Clock Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
I2C0_EN : I2C0 Clock Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
I2C1_EN : I2C1 Clock Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
PWDT0_EN : PWDT0 Clock Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
PWM0_EN : PWM0 Clock Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
PWM1_EN : PWM1 Clock Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
TIMER_EN : TIMER Clock Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
RTC_EN : RTC Clock Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
DMA0_EN : DMA0 Clock Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
GPIO_EN : GPIO Clock Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
WDG_EN : WDG Clock Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
CRC_EN : CRC Clock Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
CAN0_EN : CAN0 Clock Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
Periph Clock Enable Control 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTU_EN : CTU APB Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
ADC0_EN : ADC0 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
ACMP0_EN : ACMP0 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
PWDT1_EN : PWDT1 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Disable
#1 : 1
Clock Enable
End of enumeration elements list.
MCU System PLL Config 0
address_offset : 0x8890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSPLL1_FBKDIV : Feedback-Divider
bits : 15 - 22 (8 bit)
access : read-write
SYSPLL1_POSDIV : Post-divider Ratio
bits : 25 - 29 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
NONE
#00001 : 00001
VCO/2
#00010 : 00010
VCO/4
#00011 : 00011
VCO/6
#00100 : 00100
VCO/8
#00101 : 00101
VCO/10
#00110 : 00110
VCO/12
#00111 : 00111
VCO/14
#01000 : 01000
VCO/16
#01001 : 01001
VCO/18
#01010 : 01010
VCO/20
#01011 : 01011
VCO/22
#01100 : 01100
VCO/24
#01101 : 01101
VCO/26
#01110 : 01110
VCO/28
#01111 : 01111
VCO/30
#10000 : 10000
VCO/32
#10001 : 10001
VCO/34
#10010 : 10010
VCO/36
#10011 : 10011
VCO/38
#10100 : 10100
VCO/40
#10101 : 10101
VCO/42
#10110 : 10110
VCO/44
#10111 : 10111
VCO/46
#11000 : 11000
VCO/48
#11001 : 11001
VCO/50
#11010 : 11010
VCO/52
#11011 : 11011
VCO/54
#11100 : 11100
VCO/56
#11101 : 11101
VCO/58
#11110 : 11110
VCO/60
#11111 : 11111
VCO/62
End of enumeration elements list.
SYSPLL1_PREDIV : Pre-Divider
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Fref=Fin/1
#01 : 01
Fref=Fin/2
#10 : 10
Fref=Fin/4
End of enumeration elements list.
MCU Reset Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXT_RST_DEGLITCH_EN : EXT Reset Deglitch Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Deglitch Disable
#1 : 1
Deglitch Enable
End of enumeration elements list.
EXT_RST_DEGLITCH_VALUE : Deglitch Value Set
bits : 1 - 7 (7 bit)
access : read-write
PLL_UNLOCK_RST_EN : PLL Unlock Reset Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ECC2_RST_EN : ECC2 Error Reset Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CPU_SYSRST_EN : CPU System Reset Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
CPU_LOCKUP_RST_EN : CPU Lockup Reset Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
XOSC_LOSS_RST_EN : XOSC Loss Reset Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.