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UART0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection :

Registers

RBR

LCR1

FCR

EFR

IER

LSR0

LSR1

SMP_CNT

GUARD

SLEEP_EN

DIV_L

DMA_EN

DIV_FRAC

RS485CR

CNTR

IDLE

LINCR

BRKLGH

DIV_H

LCR0


RBR

RX/TX Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBR RBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RBR_THR

RBR_THR : RX/TX Data Register
bits : 0 - 8 (9 bit)
access : read-write


LCR1

uart control register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR1 LCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN TXEN LOOP WLS2 INVRX INVTX

RXEN : uart receiver enable
bits : 0 - 0 (1 bit)
access : read-write

TXEN : uart Transmitter enable
bits : 1 - 1 (1 bit)
access : read-write

LOOP : uart loop back mode enable
bits : 4 - 4 (1 bit)
access : read-write

WLS2 : uart 9 bit data mode enable/disable bit
bits : 5 - 5 (1 bit)
access : read-write

INVRX : uart rx input inverse enable/disable bit
bits : 6 - 6 (1 bit)
access : read-write

INVTX : uart tx output inverse enable/disable bit
bits : 7 - 7 (1 bit)
access : read-write


FCR

FIFO Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOE

FIFOE : RX and TX FIFO enable/disable bit
bits : 0 - 0 (1 bit)
access : read-write


EFR

hardware flow control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EFR EFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTS CTS

RTS : hardware reception flow control enable/disable bit
bits : 6 - 6 (1 bit)
access : read-write

CTS : hardware transmiison flow control enable/disable bit
bits : 7 - 7 (1 bit)
access : read-write


IER

Interrupt Enable register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERXNE ETXE ETC EPE EFE ENE EOEBI EDCTS ETXDF

ERXNE : receiving data not empty interrupt enable bit
bits : 0 - 0 (1 bit)
access : read-write

ETXE : transmitting data empty interrupt enable bit
bits : 1 - 1 (1 bit)
access : read-write

ETC : transmitting completed interrupt enable bit
bits : 2 - 2 (1 bit)
access : read-write

EPE : parity error interrupt enable bit
bits : 3 - 3 (1 bit)
access : read-write

EFE : overflow or frame error interrupt enable bit
bits : 4 - 4 (1 bit)
access : read-write

ENE : noise error interrupt enable bit
bits : 5 - 5 (1 bit)
access : read-write

EOEBI : overflow error or break error interrupt enable bit
bits : 6 - 6 (1 bit)
access : read-write

EDCTS : CTS_n changing interrupt enable bit
bits : 7 - 7 (1 bit)
access : read-write

ETXDF : TX register or TX FIFO full interrupt enable bit
bits : 8 - 8 (1 bit)
access : read-write


LSR0

Line Status Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSR0 LSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR OE PE FE BI THRE TC NE TXDF

DR : Data ready flag
bits : 0 - 0 (1 bit)
access : read-write

OE : overrun error flag
bits : 1 - 1 (1 bit)
access : read-write

PE : parity error flag
bits : 2 - 2 (1 bit)
access : read-write

FE : frame error flag
bits : 3 - 3 (1 bit)
access : read-write

BI : break error flag
bits : 4 - 4 (1 bit)
access : read-write

THRE : TX holding register or TX FIFO empty flag
bits : 5 - 5 (1 bit)
access : read-write

TC : Transmitting finished flag
bits : 6 - 6 (1 bit)
access : read-write

NE : noise error flag
bits : 7 - 7 (1 bit)
access : read-write

TXDF : TX register or TX FIFO full flag
bits : 8 - 8 (1 bit)
access : read-write


LSR1

Line Status Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSR1 LSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDLE SYNERR FBRK DCTS BRKWAK UART_IDLE CTS RTS

IDLE : IDLE flag
bits : 0 - 0 (1 bit)
access : read-write

SYNERR : SYNERR flag
bits : 1 - 1 (1 bit)
access : read-write

FBRK : LIN break occurrer flag
bits : 2 - 2 (1 bit)
access : read-write

DCTS : Pin CTS_n signal changing flag
bits : 3 - 3 (1 bit)
access : read-write

BRKWAK : LIN BREAK wakeup flag
bits : 4 - 4 (1 bit)
access : read-write

UART_IDLE : UART IDLE
bits : 5 - 5 (1 bit)
access : read-write

CTS : Hardware flow status - CTS
bits : 6 - 6 (1 bit)
access : read-write

RTS : Hardware flow status - RTS
bits : 7 - 7 (1 bit)
access : read-write


SMP_CNT

uart sample counter register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMP_CNT SMP_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP_CNT

SMP_CNT : uart sample counter
bits : 0 - 1 (2 bit)
access : read-write


GUARD

uart guard time register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GUARD GUARD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GUARD_CNT GUARD_EN

GUARD_CNT : Guard interval count value
bits : 0 - 3 (4 bit)
access : read-write

GUARD_EN : Guard interval time added enabling signal
bits : 4 - 4 (1 bit)
access : read-write


SLEEP_EN

uart sleep enable register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEP_EN SLEEP_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEP_EN

SLEEP_EN : uart sleep function enable bit
bits : 0 - 0 (1 bit)
access : read-write


DIV_L

Divisor low 8 bits register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_L DIV_L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_L

DIV_L : uart baud rate divisor low 8 bits
bits : 0 - 7 (8 bit)
access : read-write


DMA_EN

uart DMA enable register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_EN DMA_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_DMA_EN TX_DMA_EN

RX_DMA_EN : uart RX DMA enable bit
bits : 0 - 0 (1 bit)
access : read-write

TX_DMA_EN : uart TX DMA enable bit
bits : 1 - 1 (1 bit)
access : read-write


DIV_FRAC

Uart Fractional Divider Address
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_FRAC DIV_FRAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_FRAC

DIV_FRAC : uart fractional divider
bits : 0 - 7 (8 bit)
access : read-write


RS485CR

Uart RS485 control register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RS485CR RS485CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLYEN INVPOL RS485EN

DLYEN : Delay insert between the last stop bit and rts_n or dtr_n de-assertion
bits : 4 - 4 (1 bit)
access : read-write

INVPOL : inverse the polarity of rts_n
bits : 5 - 5 (1 bit)
access : read-write

RS485EN : RS485 mode enable bit
bits : 7 - 7 (1 bit)
access : read-write


CNTR

Uart Counter time delay in RS485 mode
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTR

CNTR : Uart Counter time delay in RS485 mode
bits : 0 - 7 (8 bit)
access : read-write


IDLE

Uart IDLE register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDLE IDLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDLEIE ILEN

IDLEIE : IDLE interrupt enable bit
bits : 4 - 4 (1 bit)
access : read-write

ILEN : Bus idle detect enable/disable
bits : 7 - 7 (1 bit)
access : read-write


LINCR

LIN Control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LINCR LINCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRKWAKIE SYNERRIE LABAUDEN SDBRK LBRKDL LBRKIE LINEN

BRKWAKIE : Break wakeup interrupt enable/disable
bits : 1 - 1 (1 bit)
access : read-write

SYNERRIE : Synch byte error interrupt enable/disable
bits : 2 - 2 (1 bit)
access : read-write

LABAUDEN : 0x55 used as automatic baudrate detection enable/disable
bits : 3 - 3 (1 bit)
access : read-write

SDBRK : Lin mode transfer 13 zero enable/disable
bits : 4 - 4 (1 bit)
access : read-write

LBRKDL : Lin break length detection interrupt enable/disable
bits : 5 - 5 (1 bit)
access : read-write

LBRKIE : Lin break byte detection interrupt enable/disable
bits : 6 - 6 (1 bit)
access : read-write

LINEN : Lin mode interrupt enable/disable
bits : 7 - 7 (1 bit)
access : read-write


BRKLGH

LIN Break Length Select Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRKLGH BRKLGH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRKLGH

BRKLGH : Break length
bits : 0 - 3 (4 bit)
access : read-write


DIV_H

Divisor high 8 bits register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIV_H DIV_H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_H

DIV_H : uart baud rate divisor high 8 bits
bits : 0 - 7 (8 bit)
access : read-write


LCR0

uart control register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCR0 LCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WLS1_WLS0 STB PEN EPS SP SUB

WLS1_WLS0 : uart data mode select bits
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 5_BIT

5 BITS

#01 : 6_BIT

6 BITS

#10 : 7_BIT

7 BITS

#11 : 8_BIT

8 BITS

End of enumeration elements list.

STB : Number of STOP bits
bits : 2 - 2 (1 bit)
access : read-write

PEN : uart parity enable/disable bit
bits : 3 - 3 (1 bit)
access : read-write

EPS : odd/eveen number select bit
bits : 4 - 4 (1 bit)
access : read-write

SP : stick parity
bits : 5 - 5 (1 bit)
access : read-write

SUB : Sets up break
bits : 6 - 6 (1 bit)
access : read-write



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