\n
address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection :
RX/TX Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBR_THR : RX/TX Data Register
bits : 0 - 8 (9 bit)
access : read-write
uart control register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXEN : uart receiver enable
bits : 0 - 0 (1 bit)
access : read-write
TXEN : uart Transmitter enable
bits : 1 - 1 (1 bit)
access : read-write
LOOP : uart loop back mode enable
bits : 4 - 4 (1 bit)
access : read-write
WLS2 : uart 9 bit data mode enable/disable bit
bits : 5 - 5 (1 bit)
access : read-write
INVRX : uart rx input inverse enable/disable bit
bits : 6 - 6 (1 bit)
access : read-write
INVTX : uart tx output inverse enable/disable bit
bits : 7 - 7 (1 bit)
access : read-write
FIFO Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOE : RX and TX FIFO enable/disable bit
bits : 0 - 0 (1 bit)
access : read-write
hardware flow control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTS : hardware reception flow control enable/disable bit
bits : 6 - 6 (1 bit)
access : read-write
CTS : hardware transmiison flow control enable/disable bit
bits : 7 - 7 (1 bit)
access : read-write
Interrupt Enable register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERXNE : receiving data not empty interrupt enable bit
bits : 0 - 0 (1 bit)
access : read-write
ETXE : transmitting data empty interrupt enable bit
bits : 1 - 1 (1 bit)
access : read-write
ETC : transmitting completed interrupt enable bit
bits : 2 - 2 (1 bit)
access : read-write
EPE : parity error interrupt enable bit
bits : 3 - 3 (1 bit)
access : read-write
EFE : overflow or frame error interrupt enable bit
bits : 4 - 4 (1 bit)
access : read-write
ENE : noise error interrupt enable bit
bits : 5 - 5 (1 bit)
access : read-write
EOEBI : overflow error or break error interrupt enable bit
bits : 6 - 6 (1 bit)
access : read-write
EDCTS : CTS_n changing interrupt enable bit
bits : 7 - 7 (1 bit)
access : read-write
ETXDF : TX register or TX FIFO full interrupt enable bit
bits : 8 - 8 (1 bit)
access : read-write
Line Status Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : Data ready flag
bits : 0 - 0 (1 bit)
access : read-write
OE : overrun error flag
bits : 1 - 1 (1 bit)
access : read-write
PE : parity error flag
bits : 2 - 2 (1 bit)
access : read-write
FE : frame error flag
bits : 3 - 3 (1 bit)
access : read-write
BI : break error flag
bits : 4 - 4 (1 bit)
access : read-write
THRE : TX holding register or TX FIFO empty flag
bits : 5 - 5 (1 bit)
access : read-write
TC : Transmitting finished flag
bits : 6 - 6 (1 bit)
access : read-write
NE : noise error flag
bits : 7 - 7 (1 bit)
access : read-write
TXDF : TX register or TX FIFO full flag
bits : 8 - 8 (1 bit)
access : read-write
Line Status Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDLE : IDLE flag
bits : 0 - 0 (1 bit)
access : read-write
SYNERR : SYNERR flag
bits : 1 - 1 (1 bit)
access : read-write
FBRK : LIN break occurrer flag
bits : 2 - 2 (1 bit)
access : read-write
DCTS : Pin CTS_n signal changing flag
bits : 3 - 3 (1 bit)
access : read-write
BRKWAK : LIN BREAK wakeup flag
bits : 4 - 4 (1 bit)
access : read-write
UART_IDLE : UART IDLE
bits : 5 - 5 (1 bit)
access : read-write
CTS : Hardware flow status - CTS
bits : 6 - 6 (1 bit)
access : read-write
RTS : Hardware flow status - RTS
bits : 7 - 7 (1 bit)
access : read-write
uart sample counter register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMP_CNT : uart sample counter
bits : 0 - 1 (2 bit)
access : read-write
uart guard time register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GUARD_CNT : Guard interval count value
bits : 0 - 3 (4 bit)
access : read-write
GUARD_EN : Guard interval time added enabling signal
bits : 4 - 4 (1 bit)
access : read-write
uart sleep enable register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEP_EN : uart sleep function enable bit
bits : 0 - 0 (1 bit)
access : read-write
Divisor low 8 bits register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_L : uart baud rate divisor low 8 bits
bits : 0 - 7 (8 bit)
access : read-write
uart DMA enable register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_DMA_EN : uart RX DMA enable bit
bits : 0 - 0 (1 bit)
access : read-write
TX_DMA_EN : uart TX DMA enable bit
bits : 1 - 1 (1 bit)
access : read-write
Uart Fractional Divider Address
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_FRAC : uart fractional divider
bits : 0 - 7 (8 bit)
access : read-write
Uart RS485 control register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLYEN : Delay insert between the last stop bit and rts_n or dtr_n de-assertion
bits : 4 - 4 (1 bit)
access : read-write
INVPOL : inverse the polarity of rts_n
bits : 5 - 5 (1 bit)
access : read-write
RS485EN : RS485 mode enable bit
bits : 7 - 7 (1 bit)
access : read-write
Uart Counter time delay in RS485 mode
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTR : Uart Counter time delay in RS485 mode
bits : 0 - 7 (8 bit)
access : read-write
Uart IDLE register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDLEIE : IDLE interrupt enable bit
bits : 4 - 4 (1 bit)
access : read-write
ILEN : Bus idle detect enable/disable
bits : 7 - 7 (1 bit)
access : read-write
LIN Control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKWAKIE : Break wakeup interrupt enable/disable
bits : 1 - 1 (1 bit)
access : read-write
SYNERRIE : Synch byte error interrupt enable/disable
bits : 2 - 2 (1 bit)
access : read-write
LABAUDEN : 0x55 used as automatic baudrate detection enable/disable
bits : 3 - 3 (1 bit)
access : read-write
SDBRK : Lin mode transfer 13 zero enable/disable
bits : 4 - 4 (1 bit)
access : read-write
LBRKDL : Lin break length detection interrupt enable/disable
bits : 5 - 5 (1 bit)
access : read-write
LBRKIE : Lin break byte detection interrupt enable/disable
bits : 6 - 6 (1 bit)
access : read-write
LINEN : Lin mode interrupt enable/disable
bits : 7 - 7 (1 bit)
access : read-write
LIN Break Length Select Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKLGH : Break length
bits : 0 - 3 (4 bit)
access : read-write
Divisor high 8 bits register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_H : uart baud rate divisor high 8 bits
bits : 0 - 7 (8 bit)
access : read-write
uart control register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS1_WLS0 : uart data mode select bits
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 5_BIT
5 BITS
#01 : 6_BIT
6 BITS
#10 : 7_BIT
7 BITS
#11 : 8_BIT
8 BITS
End of enumeration elements list.
STB : Number of STOP bits
bits : 2 - 2 (1 bit)
access : read-write
PEN : uart parity enable/disable bit
bits : 3 - 3 (1 bit)
access : read-write
EPS : odd/eveen number select bit
bits : 4 - 4 (1 bit)
access : read-write
SP : stick parity
bits : 5 - 5 (1 bit)
access : read-write
SUB : Sets up break
bits : 6 - 6 (1 bit)
access : read-write
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