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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x34 byte (0x0)
mem_usage : registers
protection :

Registers

ADDR0

CTRL0

CTRL1

CTRL2

CTRL3

STATUS0

STATUS1

DGLCFG

DATA

STARTSTOP

ADDR1

SAMPLE_CNT

STEP_CNT


ADDR0

Address Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR0 ADDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD

AD : 7Bit Address
bits : 1 - 7 (7 bit)
access : read-write


CTRL0

Control Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUEN TACK TX MSTR IICIE IICEN

WUEN : wakeup enable
bits : 2 - 2 (1 bit)
access : read-write

TACK : Transmit Acknowledge Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACK will sent to the bus on the following receiving byte

#1 : 1

NACK will sent to the bus on the following receiving byte

End of enumeration elements list.

TX : Master Transmit Direction Select
bits : 4 - 4 (1 bit)
access : read-write

MSTR : I2C operation mode Select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Slave Mode

#1 : 1

Master Mode

End of enumeration elements list.

IICIE : I2C interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

IICEN : I2C Module Enable
bits : 7 - 7 (1 bit)
access : read-write


CTRL1

Control Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STREN ARBEN SYNCEN ADEXT GCAEN

STREN : Slave SCL Strech Enable
bits : 0 - 0 (1 bit)
access : read-write

ARBEN : Arbitration Enable
bits : 3 - 3 (1 bit)
access : read-write

SYNCEN : SCL Sync Enable
bits : 4 - 4 (1 bit)
access : read-write

ADEXT : Slave Address Extension
bits : 6 - 6 (1 bit)
access : read-write

GCAEN : Slave General Call Enable
bits : 7 - 7 (1 bit)
access : read-write


CTRL2

Control Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MNTEN NACKIE TXEMIE RXFIE TXUFIE RXOFIE

MNTEN : Slave Monitor Function Enable
bits : 0 - 0 (1 bit)
access : read-write

NACKIE : NACK Get Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

TXEMIE : Slave TX Buffer Empty Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

RXFIE : Slave RX Buffer Full Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

TXUFIE : Slave TX Buffer Underflow Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

RXOFIE : Slave RX Buffer Overflow Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write


CTRL3

Control Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMATXEN DMARXEN

DMATXEN : DMATX Enable
bits : 0 - 0 (1 bit)
access : read-write

DMARXEN : DMARX Enable
bits : 1 - 1 (1 bit)
access : read-write


STATUS0

Status Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS0 STATUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RACK SRW READY ARBLOST BUSY SAMF BND

RACK : Acknowledge Received(master or slave TX mode)
bits : 0 - 0 (1 bit)
access : read-write

SRW : Slave Read/Write Direction
bits : 2 - 2 (1 bit)
access : read-only

READY : Internal Hardware Core Is Ready For New Command or Not
bits : 3 - 3 (1 bit)
access : read-only

ARBLOST : Arbitration Lost Flag
bits : 4 - 4 (1 bit)
access : read-write

BUSY : Indicates The Status of The Bus in Slave/Master
bits : 5 - 5 (1 bit)
access : read-only

SAMF : Slave Address Match Flag
bits : 6 - 6 (1 bit)
access : read-write

BND : Byte Tx End Flag(include ACK bit, 9 SCL)
bits : 7 - 7 (1 bit)
access : read-write


STATUS1

Status Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS1 STATUS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEF RXFF TXUF RXOF

TXEF : Slave TX Buffer Empty Flag
bits : 0 - 0 (1 bit)
access : read-write

RXFF : Slave RX Buffer Full flag
bits : 1 - 1 (1 bit)
access : read-write

TXUF : Slave TX Buffer Underflow Flag
bits : 2 - 2 (1 bit)
access : read-write

RXOF : Slave RX Buffer Overflow Flag
bits : 3 - 3 (1 bit)
access : read-write


DGLCFG

Deglitch Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGLCFG DGLCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DGL_CNT STARTF SSIE STOPF DGLEN

DGL_CNT : Deglitch Counter
bits : 0 - 3 (4 bit)
access : read-write

STARTF : I2C Bus Start Flag
bits : 4 - 4 (1 bit)
access : read-write

SSIE : I2C Bus START or STOP Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

STOPF : I2C Bus Stop Flag
bits : 6 - 6 (1 bit)
access : read-write

DGLEN : I2C Deglitch Filter Enable
bits : 7 - 7 (1 bit)
access : read-write


DATA

Data Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA MAK

DATA : Data
bits : 0 - 7 (8 bit)
access : read-write

MAK : Slave Monitor Function ACK bit
bits : 8 - 8 (1 bit)
access : read-only


STARTSTOP

START_STOP Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STARTSTOP STARTSTOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP

START : Master Send Start Signal
bits : 0 - 0 (1 bit)
access : read-write

STOP : Matsre Send I2C Stop Signal
bits : 1 - 1 (1 bit)
access : read-write


ADDR1

Address register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR1 ADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD RAD RMEN

AD : 10Bit Address
bits : 0 - 2 (3 bit)
access : read-write

RAD : 7bit Range Address
bits : 4 - 10 (7 bit)
access : read-write

RMEN : 7bit Range Enable
bits : 12 - 12 (1 bit)
access : read-write


SAMPLE_CNT

SAMPLE_CNT Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPLE_CNT SAMPLE_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPLE_CNT

SAMPLE_CNT : Adjust the width of each sample
bits : 0 - 7 (8 bit)
access : read-write


STEP_CNT

STEP_CNT Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STEP_CNT STEP_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP_CNT

STEP_CNT : Specifies the number of Samples per half pulse width
bits : 0 - 7 (8 bit)
access : read-write



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