\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
SPI Configuration Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCK_HIGH : SCK High Count
bits : 0 - 7 (8 bit)
access : read-write
SCK_LOW : SCK low count
bits : 8 - 15 (8 bit)
access : read-write
CS_HOLD : CS hold count
bits : 16 - 23 (8 bit)
access : read-write
CS_SETUP : CS Setup Count
bits : 24 - 31 (8 bit)
access : read-write
SPI Data Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 15 (16 bit)
access : read-write
SPI configuration register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MNOV : Master No Overflow mode enable bit
bits : 1 - 1 (1 bit)
access : read-write
TOEN : TX only mode enable bit
bits : 2 - 2 (1 bit)
access : read-write
ROEN : RX only mode enable bit
bits : 3 - 3 (1 bit)
access : read-write
SPI Configuration Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS_IDLE : CS idle count
bits : 0 - 7 (8 bit)
access : read-write
TXEIE : TX buffer empty interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
RXFIE : RX buffer full interrupt enable
bits : 9 - 9 (1 bit)
access : read-write
TXUIE : TX buffer underflow interrupt enable
bits : 10 - 10 (1 bit)
access : read-write
RXOIE : RX buffer overflow interrupt enable
bits : 11 - 11 (1 bit)
access : read-write
MSTR : master/slave mode selection
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : SLAVE
SPI slave mode
1 : MASTER
SPI master mode
End of enumeration elements list.
MODFIE : mode fault interrupt enable
bits : 13 - 13 (1 bit)
access : read-write
DMATXEN : DMA TX channel enable
bits : 14 - 14 (1 bit)
access : read-write
DMARXEN : DMA RX channel enable
bits : 15 - 15 (1 bit)
access : read-write
CPOL : clock polarity
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : CPOL_0
SCK is 0 when idle
1 : CPOL_1
SCK is 1 when idle
End of enumeration elements list.
CPHA : clock phase
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : CPHA_0
the second SCK transition is the first data capture edge
1 : CPHA_1
the first SCK transition is the first data capture edge
End of enumeration elements list.
MSBF : TX MSB first Select
bits : 18 - 18 (1 bit)
access : read-write
RMSBF : RX MSB first Select
bits : 19 - 19 (1 bit)
access : read-write
FRMSIZE : frame size
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 4BIT
Frame size is 4 bits
#0001 : 4BIT
Frame size is 4 bits
#0010 : 4BIT
Frame size is 4 bits
#0011 : 4BIT
Frame size is 4 bits
#0100 : 5BIT
Frame size is 5 bits
#0101 : 6BIT
Frame size is 6 bits
#0110 : 7BIT
Frame size is 7 bits
#0111 : 8BIT
Frame size is 8 bits
#1000 : 9BIT
Frame size is 9 bits
#1001 : 10BIT
Frame size is 10 bits
#1010 : 11BIT
Frame size is 11 bits
#1011 : 12BIT
Frame size is 12 bits
#1100 : 13BIT
Frame size is 13 bits
#1101 : 14BIT
Frame size is 14 bits
#1110 : 15BIT
Frame size is 15 bits
#1111 : 16BIT
Frame size is 16 bits
End of enumeration elements list.
CSOE : CS hardware output enable
bits : 25 - 25 (1 bit)
access : read-write
MODFEN : mode fault detect enable
bits : 26 - 26 (1 bit)
access : read-write
CONT_CS : CS continuous output enable
bits : 28 - 28 (1 bit)
access : read-write
WKUEN : wake up function enable(only valid for slave mode)
bits : 30 - 30 (1 bit)
access : read-write
SPI Command Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Enable
bits : 0 - 0 (1 bit)
access : read-write
SWRST : software reset
bits : 4 - 4 (1 bit)
access : read-write
CSRLS : CS release(only valid for CS continuous output)
bits : 5 - 5 (1 bit)
access : read-write
ROTRIG : Master RX only mode edge
bits : 6 - 6 (1 bit)
access : read-write
SPI Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEF : TX buffer empty flag
bits : 0 - 0 (1 bit)
access : read-write
RXFF : RX buffer Full flag
bits : 1 - 1 (1 bit)
access : read-write
TXUF : TX buffer underflow flag
bits : 2 - 2 (1 bit)
access : read-write
RXOF : RX buffer overflow flag
bits : 3 - 3 (1 bit)
access : read-write
MODEF : Mode error flag
bits : 4 - 4 (1 bit)
access : read-write
MEBY : SPI master engine busy flag
bits : 7 - 7 (1 bit)
access : read-write
IDLEF : SPI IDLE flag
bits : 8 - 8 (1 bit)
access : read-write
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