\n

ADC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection :

Registers

STR

SPT1

IOFR0

IOFR1

IOFR2

IOFR3

AMOHR

AMOLR

RSQR0

RSQR1

RSQR2

ISQR

IDR0

CTRL0

IDR1

IDR2

IDR3

RDR

CTRL1

SPT0


STR

ADC status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STR STR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMO EOC IEOC IDLE NAMO AAMO

AMO : Analog monitor event occurs(Level mode)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No analog monitor event

#1 : 1

Analog monitor event occurs

End of enumeration elements list.

EOC : Regular group conversion completed flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Regular group conversion not completed

#1 : 1

Regular group conversion completed

End of enumeration elements list.

IEOC : Injection group conversion completed flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Injection group conversion not completed

#1 : 1

Injection group conversion completed

End of enumeration elements list.

IDLE : ADC idle status indicate
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Busy status

#1 : 1

Idle status

End of enumeration elements list.

NAMO : Analog monitor normal event occurs(Edge mode)
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No analog monitor event

#1 : 1

Analog monitor normal event occurs

End of enumeration elements list.

AAMO : Analog monitor Abnormal event occurs(Edge mode)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No analog monitor event

#1 : 1

Analog monitor abnormal event occurs

End of enumeration elements list.


SPT1

ADC Sample time setting register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPT1 SPT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPT0 SPT1 SPT2 SPT3 SPT4 SPT5 SPT6 SPT7 SPT8 SPT9

SPT0 : Sample time for Channel 0
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT1 : Sample time for Channel 1
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT2 : Sample time for Channel 2
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT3 : Sample time for Channel 3
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT4 : Sample time for Channel 4
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT5 : Sample time for Channel 5
bits : 15 - 17 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT6 : Sample time for Channel 6
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT7 : Sample time for Channel 7
bits : 21 - 23 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT8 : Sample time for Channel 8
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT9 : Sample time for Channel 9
bits : 27 - 29 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.


IOFR0

ADC Injection Group Offset Register(n)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFR0 IOFR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOFR

IOFR : Injection group offset Value
bits : 0 - 11 (12 bit)
access : read-write


IOFR1

ADC Injection Group Offset Register(n)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFR1 IOFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOFR

IOFR : Injection group offset Value
bits : 0 - 11 (12 bit)
access : read-write


IOFR2

ADC Injection Group Offset Register(n)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFR2 IOFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOFR

IOFR : Injection group offset Value
bits : 0 - 11 (12 bit)
access : read-write


IOFR3

ADC Injection Group Offset Register(n)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFR3 IOFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOFR

IOFR : Injection group offset Value
bits : 0 - 11 (12 bit)
access : read-write


AMOHR

AMO High threshold and offset register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMOHR AMOHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOHT AMOHO

AMOHT : AMO High threshold value
bits : 0 - 11 (12 bit)
access : read-write

AMOHO : High offset value
bits : 16 - 27 (12 bit)
access : read-write


AMOLR

AMO Low threshold and offset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMOLR AMOLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOLT AMOLO

AMOLT : AMO Low threshold value
bits : 0 - 11 (12 bit)
access : read-write

AMOLO : Low offset value
bits : 16 - 27 (12 bit)
access : read-write


RSQR0

ADC regular group sequence configure register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQR0 RSQR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSQ12 RSQ13 RSQL

RSQ12 : channel selection for regular group 12
bits : 0 - 4 (5 bit)
access : read-write

RSQ13 : channel selection for regular group 13
bits : 5 - 9 (5 bit)
access : read-write

RSQL : Length of regular group
bits : 20 - 23 (4 bit)
access : read-write


RSQR1

ADC regular group sequence configure register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQR1 RSQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSQ6 RSQ7 RSQ8 RSQ9 RSQ10 RSQ11

RSQ6 : channel selection for regular group 6
bits : 0 - 4 (5 bit)
access : read-write

RSQ7 : channel selection for regular group 7
bits : 5 - 9 (5 bit)
access : read-write

RSQ8 : channel selection for regular group 8
bits : 10 - 14 (5 bit)
access : read-write

RSQ9 : channel selection for regular group 9
bits : 15 - 19 (5 bit)
access : read-write

RSQ10 : channel selection for regular group 10
bits : 20 - 24 (5 bit)
access : read-write

RSQ11 : channel selection for regular group 11
bits : 25 - 29 (5 bit)
access : read-write


RSQR2

ADC regular group sequence configure register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQR2 RSQR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSQ0 RSQ1 RSQ2 RSQ3 RSQ4 RSQ5

RSQ0 : channel selection for regular group 0
bits : 0 - 4 (5 bit)
access : read-write

RSQ1 : channel selection for regular group 1
bits : 5 - 9 (5 bit)
access : read-write

RSQ2 : channel selection for regular group 2
bits : 10 - 14 (5 bit)
access : read-write

RSQ3 : channel selection for regular group 3
bits : 15 - 19 (5 bit)
access : read-write

RSQ4 : channel selection for regular group 4
bits : 20 - 24 (5 bit)
access : read-write

RSQ5 : channel selection for regular group 5
bits : 25 - 29 (5 bit)
access : read-write


ISQR

ADC injection group sequence configure register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISQR ISQR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISQ0 ISQ1 ISQ2 ISQ3 ISQL

ISQ0 : channel selection for injection group 0
bits : 0 - 4 (5 bit)
access : read-write

ISQ1 : channel selection for injection group 1
bits : 5 - 9 (5 bit)
access : read-write

ISQ2 : channel selection for injection group 2
bits : 10 - 14 (5 bit)
access : read-write

ISQ3 : channel selection for injection group 3
bits : 15 - 19 (5 bit)
access : read-write

ISQL : length of injection group
bits : 20 - 21 (2 bit)
access : read-write


IDR0

ADC Injection Group data Register(n)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDR0 IDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDR

IDR : Injection group data Value
bits : 0 - 11 (12 bit)
access : read-only


CTRL0

ADC Control Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMOCH AMOSGL IAMOEN AMOEN DISCNUM IAUTO IDISCEN DISCEN CONT SCAN EOCIE IEOCIE AMOIE DMAEN EXTTRIG IEXTTRIG ALIGN AMOMODE INTERVAL ISWSTART SWSTART

AMOCH : Analog monitor detecting channel
bits : 0 - 4 (5 bit)
access : read-write

AMOSGL : Analog monitor detecting channel
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

AMO used in All channels

#1 : 1

AMO function used in single channel defined in AMOCH register

End of enumeration elements list.

IAMOEN : Injection Group Analog Monitor Detect function Enable
bits : 6 - 6 (1 bit)
access : read-write

AMOEN : Regular Group Analog Monitor Detect function Enable
bits : 7 - 7 (1 bit)
access : read-write

DISCNUM : Discontinuous conversion length of channel
bits : 8 - 10 (3 bit)
access : read-write

IAUTO : Injection Group Automatic conversion
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Injection group automatic conversion disabled

#1 : 1

Injection group automatic conversion enabled

End of enumeration elements list.

IDISCEN : Discontinous mode on injected channels
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Injection group Discontinous mode disabled

#1 : 1

Injection group Discontinous mode enabled

End of enumeration elements list.

DISCEN : Discontinous mode on regular channels
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Regular group Discontinous mode disabled

#1 : 1

Regular group Discontinous mode enabled

End of enumeration elements list.

CONT : Continuous conversion
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Single conversion mode

#1 : 1

Continuous conversion mode

End of enumeration elements list.

SCAN : Scan Mode
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Scan mode disabled

#1 : 1

Scan mode enabled

End of enumeration elements list.

EOCIE : EOC interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

EOC interrupt Disabled

#1 : 1

EOC interrupt Enabled, An interrupt is generated when the EOC bit is set

End of enumeration elements list.

IEOCIE : IEOC interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

IEOC interrupt Disabled

#1 : 1

IEOC interrupt Enabled, An interrupt is generated when the IEOC bit is set

End of enumeration elements list.

AMOIE : AMO interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

AMO interrupt Disabled

#1 : 1

AMO interrupt Enabled, An interrupt is generated when the AMO bit is set

End of enumeration elements list.

DMAEN : DMA Function Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA function Disabled

#1 : 1

DMA function Enabled

End of enumeration elements list.

EXTTRIG : Regular group trig source select
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal trigger source(software trig)

#1 : 1

External trigger source

End of enumeration elements list.

IEXTTRIG : Inject group trig source select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal trigger source(software trig)

#1 : 1

External trigger source

End of enumeration elements list.

ALIGN : Data Alignment
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Right Alignment

#1 : 1

Left Alignment

End of enumeration elements list.

AMOMODE : Analog monitor type
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Level mode

#1 : 1

Edge mode

End of enumeration elements list.

INTERVAL : Interval mode
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Interval mode

End of enumeration elements list.

ISWSTART : Software trigger for Inject channels
bits : 30 - 30 (1 bit)
access : read-write

SWSTART : Software trigger for regular channels
bits : 31 - 31 (1 bit)
access : read-write


IDR1

ADC Injection Group data Register(n)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDR1 IDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDR

IDR : Injection group data Value
bits : 0 - 11 (12 bit)
access : read-only


IDR2

ADC Injection Group data Register(n)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDR2 IDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDR

IDR : Injection group data Value
bits : 0 - 11 (12 bit)
access : read-only


IDR3

ADC Injection Group data Register(n)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDR3 IDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDR

IDR : Injection group data Value
bits : 0 - 11 (12 bit)
access : read-only


RDR

ADC Regular Group data Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDR RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDR

RDR : Regular group data Value
bits : 0 - 11 (12 bit)
access : read-only


CTRL1

ADC Control Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADON CALEN PSC

ADON : ADC converter ON/OFF
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ADC conversion

#1 : 1

Enable ADC and to start conversion

End of enumeration elements list.

CALEN : Calibration
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Calibration

#1 : 1

Enable Calibration

End of enumeration elements list.

PSC : Bus Clock prescaler
bits : 12 - 15 (4 bit)
access : read-write


SPT0

ADC Sample time setting register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPT0 SPT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPT10 SPT11 SPT12 SPT13

SPT10 : Sample time for Channel 10
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT11 : Sample time for Channel 11
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT12 : Sample time for Channel 12
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.

SPT13 : Sample time for Channel 13
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

#000 : 000

9 ADCCLK

#001 : 001

7 ADCCLK

#010 : 010

15 ADCCLK

#011 : 011

33 ADCCLK

#100 : 100

64 ADCCLK

#101 : 101

140 ADCCLK

#110 : 110

215 ADCCLK

#111 : 111

5 ADCCLK

End of enumeration elements list.



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