Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xA0 byte (0x0)
mem_usage : registers
protection :
PWM Initialize, Include Clock and Prescale Setting
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSRC : Clock Source Selection
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 00
No clock selected. This in effect disables the PWM counter.
#01 : 01
APB clock
#10 : 10
HSI clock
End of enumeration elements list.
CNTMODE : PWM Counter Mode Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Up Counting mode
#1 : 1
Up-Down Counting mode
End of enumeration elements list.
CNTOIE : PWM Counter Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CNTOF interrupts. Use software polling.
#1 : 1
Enable CNTOF interrupts. An interrupt is generated when CNTOF equals one.
End of enumeration elements list.
CNTOF : PWM Counter Overflow Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter has not overflowed.
#1 : 1
PWM counter has overflowed.
End of enumeration elements list.
CLKPSC : Prescale Factor Selection
bits : 8 - 23 (16 bit)
access : read-write
Channel (n) Value
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Match point direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Down count match
#1 : 1
Up count match
End of enumeration elements list.
ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write
ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write
MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write
MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Match point direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Down count match
#1 : 1
Up count match
End of enumeration elements list.
ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write
ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write
MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write
MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Match point direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Down count match
#1 : 1
Up count match
End of enumeration elements list.
ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write
ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write
MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write
MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Match point direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Down count match
#1 : 1
Up count match
End of enumeration elements list.
ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write
ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write
MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write
MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Match point direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Down count match
#1 : 1
Up count match
End of enumeration elements list.
ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write
ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write
MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write
MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Match point direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Down count match
#1 : 1
Up count match
End of enumeration elements list.
ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write
ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write
MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write
MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
PWM Counter Current Count Value
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Current Counter Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Value
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Match point direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Down count match
#1 : 1
Up count match
End of enumeration elements list.
ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write
ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write
MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write
MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHCVAL : Channel Count Value
bits : 0 - 15 (16 bit)
access : read-write
Counter Initial Value
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTINIT : no description available
bits : 0 - 15 (16 bit)
access : read-write
Status Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0SF : Channel 0 Status Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
CH1SF : Channel 1 Status Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
CH2SF : Channel 2 Status Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
CH3SF : Channel 3 Status Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
CH4SF : Channel 4 Status Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
CH5SF : Channel 5 Status Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
CH6SF : Channel 6 Status Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
CH7SF : Channel 7 Status Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
PWM Features(Functions) Mode Selection Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMSYNCEN : PWM Synchronization functio Enable
bits : 0 - 0 (1 bit)
access : read-write
INIT : Initialize The Channels Output
bits : 1 - 1 (1 bit)
access : read-write
WPDIS : Write Protection Enable Register
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write protection is enabled.
#1 : 1
Write protection is disabled.
End of enumeration elements list.
PWMSYNC : PWM Synchronization Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and PWM counter synchronization.
#1 : 1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and PWM counter synchronization.
End of enumeration elements list.
FAULTMODE : Fault Control Mode
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
Fault control is disabled for all channels.
#01 : 01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#10 : 10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#11 : 11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
End of enumeration elements list.
FAULTIE : Fault Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault control interrupt is disabled.
#1 : 1
Fault control interrupt is enabled.
End of enumeration elements list.
Synchronization
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MINSYNCP : Minimum Loading Point Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minimum loading point is disabled.
#1 : 1
The minimum loading point is enabled.
End of enumeration elements list.
MAXSYNCP : Maximum Loading Point Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The maximum loading point is disabled.
#1 : 1
The maximum loading point is enabled.
End of enumeration elements list.
OMSYNCP : Output Mask Synchronization Point
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#1 : 1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
End of enumeration elements list.
TRIG0 : PWM Synchronization Hardware Trigger 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
TRIG1 : PWM Synchronization Hardware Trigger 1
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
TRIG2 : PWM Synchronization Hardware Trigger 2
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
SWSYNC : PWM Synchronization Software Trigger
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger is not selected.
#1 : 1
Software trigger is selected.
End of enumeration elements list.
SYNCPOL : CHPOLR Register Synchronization
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
CHPOLR register is updated with its buffer value at all rising edges of system clock.
#1 : 1
CHPOLR register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
Initial Value For Channels Output
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OIV : Channel 0 Output Initialization Value
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH1OIV : Channel 1 Output Initialization Value
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH2OIV : Channel 2 Output Initialization Value
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH3OIV : Channel 3 Output Initialization Value
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH4OIV : Channel 4 Output Initialization Value
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH5OIV : Channel 5 Output Initialization Value
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH6OIV : Channel 6 Output Initialization Value
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH7OIV : Channel 7 Output Initialization Value
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
Output Mask Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OMEN : Channel 0 Output Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH1OMEN : Channel 1 Output Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH2OMEN : Channel 2 Output Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH3OMEN : Channel 3 Output Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH4OMEN : Channel 4 Output Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH5OMEN : Channel 5 Output Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH6OMEN : Channel 6 Output Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH7OMEN : Channel 7 Output Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
PWM Function Mode Selection
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAIR0COMBINEN : Combine Channels For Pair0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels 0 and 1 are independent.
#1 : 1
Channels 0 and 1 are combined.
End of enumeration elements list.
PAIR0COMPEN : Complement Channels for Pair0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel 1 output is the same as the channel 0 output.
#1 : 1
The channel 1 output is the complement of the channel 0 output.
End of enumeration elements list.
PAIR0DECAPEN : Dual Edge Capture Mode Enable for Pair0
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
PAIR0DECAP : Dual Edge Capture Mode Captures for Pair0
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
PAIR0DTEN : Deadtime Enable for Pair0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
PAIR0SYNCEN : Synchronization Enable for Pair0
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
PAIR0FAULTEN : Fault Control Enable for Pair0
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
PAIR1COMBINEN : Combine Channels For Pair1
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels 2 and 3 are independent.
#1 : 1
Channels 2 and 3 are combined.
End of enumeration elements list.
PAIR1COMPEN : Complement Of Channel (n) For Pair1
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel 3 output is the same as the channel 2 output.
#1 : 1
The channel 3 output is the complement of the channel 2 output.
End of enumeration elements list.
PAIR1DECAPEN : Dual Edge Capture Mode Enable For Pair1
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
PAIR1DECAP : Dual Edge Capture Mode Captures For Pair1
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
PAIR1DTEN : Deadtime Enable For Pair1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
PAIR1SYNCEN : Synchronization Enable For Pair1
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
PAIR1FAULTEN : Fault Control Enable For Pair1
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
PAIR2COMBINEN : Combine Channels For Pair2
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels 4 and 5 are independent.
#1 : 1
Channels 4 and 5 are combined.
End of enumeration elements list.
PAIR2COMPEN : Complement Of Channel (n) For Pair2
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel 5 output is the same as the channel 4 output.
#1 : 1
The channel 5 output is the complement of the channel 4 output.
End of enumeration elements list.
PAIR2DECAPEN : Dual Edge Capture Mode Enable For Pair2
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
PAIR2DECAP : Dual Edge Capture Mode Captures For Pair2
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
PAIR2DTEN : Deadtime Enable For Pair2
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
PAIR2SYNCEN : Synchronization Enable For Pair2
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
PAIR2FAULTEN : Fault Control Enable For Pair2
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
PAIR3COMBINEN : Combine Channels For Pair3
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels 6 and 7 are independent.
#1 : 1
Channels 6 and 7 are combined.
End of enumeration elements list.
PAIR3COMPEN : Complement Of Channel (n) For Pair3
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel 7 output is the same as the channel 6 output.
#1 : 1
The channel 7 output is the complement of the channel 6 output.
End of enumeration elements list.
PAIR3DECAPEN : Dual Edge Capture Mode Enable For Pair3
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
PAIR3DECAP : Dual Edge Capture Mode Captures For Pair3
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
PAIR3DTEN : Deadtime Enable For Pair3
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
PAIR3SYNCEN : Synchronization Enable For Pair3
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
PAIR3FAULTEN : Fault Control Enable For Pair3
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
Deadtime Setting Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write
DTPSC : Deadtime Prescaler Control Value
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#0x : 0x
Divide the system clock by 1.
#10 : 10
Divide the system clock by 4.
#11 : 11
Divide the system clock by 16.
End of enumeration elements list.
PWM External Trigger
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0TRIG : Channel 0 Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH1TRIG : Channel 1 Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH2TRIG : Channel 2 Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH3TRIG : Channel 3 Trigger Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH4TRIG : Channel 4 Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH5TRIG : Channel 5 Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH6TRIG : Channel 6 Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH7TRIG : Channel 7 Trigger Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
INITTRIGEN : Initialization Trigger Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of initialization trigger is disabled.
#1 : 1
The generation of initialization trigger is enabled.
End of enumeration elements list.
TRIGF : Channel Trigger Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel trigger was generated.
#1 : 1
A channel trigger was generated.
End of enumeration elements list.
Channel Output Polarity Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0POL : Channel 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
CH1POL : Channel 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
CH2POL : Channel 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
CH3POL : Channel 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
CH4POL : Channel 4 Polarity
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
CH5POL : Channel 5 Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
CH6POL : Channel 6 Polarity
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
CH7POL : Channel 7 Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
Fault Detect Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULTDF0 : Fault Detection Flag 0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTDF1 : Fault Detection Flag 1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTDF2 : Fault Detection Flag 2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTIN : Fault Inputs
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The logic OR of the enabled fault inputs is 0.
#1 : 1
The logic OR of the enabled fault inputs is 1.
End of enumeration elements list.
WPEN : Write Protection Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write protection is disabled. Write protected bits can be written.
#1 : 1
Write protection is enabled. Write protected bits cannot be written.
End of enumeration elements list.
FAULTDF : Fault Detection Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No fault condition was detected.
#1 : 1
A fault condition was detected.
End of enumeration elements list.
Input Capture Filter Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0CAPFVAL : Channel 0 Input Filter
bits : 0 - 4 (5 bit)
access : read-write
CH1CAPFVAL : Channel 1 Input Filter
bits : 5 - 9 (5 bit)
access : read-write
CH2CAPFVAL : Channel 2 Input Filter
bits : 10 - 14 (5 bit)
access : read-write
CH3CAPFVAL : Channel 3 Input Filter
bits : 15 - 19 (5 bit)
access : read-write
Fault Filter and Fault Enable Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FER0EN : Fault Input 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FER1EN : Fault Input 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FER2EN : Fault Input 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FF0EN : Fault Input 0 Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FF1EN : Fault Input 1 Filter Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FF2EN : Fault Input 2 Filter Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFVAL : Fault Input Filter
bits : 8 - 15 (8 bit)
access : read-write
PWM Counter Max Count Value Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCVR : Counter Max Count Value
bits : 0 - 15 (16 bit)
access : read-write
Quadrature Decoder Interface Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QDIEN : Quadrature Decoder Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Quadrature Decoder is Disable
#1 : 1
Quadrature Decoder is Enable
End of enumeration elements list.
CNTOFDIR : Overflow Direction
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Set on the bottom of counting
#1 : 1
Set on the top of counting
End of enumeration elements list.
QUADIR : Counting Direction
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counting direction is decreasing
#1 : 1
Counting direction is increasing
End of enumeration elements list.
QUADMODE : Quadrature Decoder Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Phase A and phase B encoding mode
#1 : 1
Count and direction encoding mode
End of enumeration elements list.
PHBPOL : Phase B Input Polarity
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity
#1 : 1
Inverted polarity
End of enumeration elements list.
PHAPOL : Phase A Input Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity
#1 : 1
Inverted polarity
End of enumeration elements list.
Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTOFNUM : Count Overflow Flag Number
bits : 0 - 6 (7 bit)
access : read-write
GTBEEN : Global Time Base Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Global time base is disabled
#1 : 1
Global time base is enabled
End of enumeration elements list.
GTBEOUT : Global Time Base Output
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Global time base signal generation is disabled
#1 : 1
Global time base signal generation is enabled
End of enumeration elements list.
EVENT0PSC : Channel0 input event prescaler
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Event divided by 1
#01 : 01
Event divided by 2
#10 : 10
Event divided by 4
#11 : 11
Event divided by 8
End of enumeration elements list.
EVENT1PSC : Channel1 input event prescaler
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
Event divided by 1
#01 : 01
Event divided by 2
#10 : 10
Event divided by 4
#11 : 11
Event divided by 8
End of enumeration elements list.
EVENT2PSC : Channel2 input event prescaler
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Event divided by 1
#01 : 01
Event divided by 2
#10 : 10
Event divided by 4
#11 : 11
Event divided by 8
End of enumeration elements list.
EVENT3PSC : Channel3 input event prescaler
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
Event divided by 1
#01 : 01
Event divided by 2
#10 : 10
Event divided by 4
#11 : 11
Event divided by 8
End of enumeration elements list.
EVENT4PSC : Channel4 input event prescaler
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Event divided by 1
#01 : 01
Event divided by 2
#10 : 10
Event divided by 4
#11 : 11
Event divided by 8
End of enumeration elements list.
EVENT5PSC : Channel5 input event prescaler
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Event divided by 1
#01 : 01
Event divided by 2
#10 : 10
Event divided by 4
#11 : 11
Event divided by 8
End of enumeration elements list.
EVENT6PSC : Channel6 input event prescaler
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
Event divided by 1
#01 : 01
Event divided by 2
#10 : 10
Event divided by 4
#11 : 11
Event divided by 8
End of enumeration elements list.
EVENT7PSC : Channel7 input event prescaler
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Event divided by 1
#01 : 01
Event divided by 2
#10 : 10
Event divided by 4
#11 : 11
Event divided by 8
End of enumeration elements list.
PWM Fault Input Polarity
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT0POL : Fault Input 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high
#1 : 1
The fault input polarity is active low
End of enumeration elements list.
FLT1POL : Fault Input 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high
#1 : 1
The fault input polarity is active low
End of enumeration elements list.
FLT2POL : Fault Input 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high
#1 : 1
The fault input polarity is active low
End of enumeration elements list.
Synchronization Configuration
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWTRIGMODESEL : Hardware Trigger Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM clears the TRIGj bit when the hardware trigger j is detected
#1 : 1
PWM does not clear the TRIGj bit when the hardware trigger j is detected
End of enumeration elements list.
CNTINC : CNTIN Register Synchronization
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#1 : 1
CNTIN register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
INVC : INVCTRL Register Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#1 : 1
INVCTRL register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
SWOC : SWOCTRL Register Synchronization
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#1 : 1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
SYNCMODE : Synchronization Mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Legacy PWM synchronization is selected.
#1 : 1
Enhanced PWM synchronization is selected.
End of enumeration elements list.
CNTVSWSYNC : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the PWM counter synchronization.
#1 : 1
The software trigger activates the PWM counter synchronization.
End of enumeration elements list.
PWMSVSWSYNC : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#1 : 1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
End of enumeration elements list.
OMVSWSYNC : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the OUTMASK register synchronization.
#1 : 1
The software trigger activates the OUTMASK register synchronization.
End of enumeration elements list.
INVSWSYNC : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the INVCTRL register synchronization.
#1 : 1
The software trigger activates the INVCTRL register synchronization.
End of enumeration elements list.
SWVSWSYNC : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the SWOCTRL register synchronization.
#1 : 1
The software trigger activates the SWOCTRL register synchronization.
End of enumeration elements list.
CNTVHWSYNC : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the PWM counter synchronization.
#1 : 1
A hardware trigger activates the PWM counter synchronization.
End of enumeration elements list.
PWMSVHWSYNC : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#1 : 1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
End of enumeration elements list.
OMVHWSYNC : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the OUTMASK register synchronization.
#1 : 1
A hardware trigger activates the OUTMASK register synchronization.
End of enumeration elements list.
INVHWSYNC : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the INVCTRL register synchronization.
#1 : 1
A hardware trigger activates the INVCTRL register synchronization.
End of enumeration elements list.
SWVHWSYNC : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the SWOCTRL register synchronization.
#1 : 1
A hardware trigger activates the SWOCTRL register synchronization.
End of enumeration elements list.
SWPOL : Channel POL synchronization is activeated by a softwaretrigger
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the POL register synchronization.
#1 : 1
The software trigger activates POL register synchronization.
End of enumeration elements list.
HWPOL : Channel POL synchronization is activeated by a hardwaretrigger
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
The hardware trigger does not activate the POL register synchronization.
#1 : 1
>The hardware trigger activates POL register synchronization.
End of enumeration elements list.
PWM Inverse Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAIR0INVEN : Pair Channels 0 Inverting Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
PAIR1INVEN : Pair Channels 1 Inverting Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
PAIR2INVEN : Pair Channels 2 Inverting Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
PAIR3INVEN : Pair Channels 3 Inverting Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
PWM CHannel Output Software Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0SWEN : Channel 0 Software Output Control Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH1SWEN : Channel 1 Software Output Control Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH2SWEN : Channel 2 Software Output Control Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH3SWEN : Channel 3 Software Output Control Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH4SWEN : Channel 4 Software Output Control Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH5SWEN : Channel 5 Software Output Control Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH6SWEN : Channel 6 Software Output Control Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH7SWEN : Channel 7 Software Output Control Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH0SWCV : Channel 0 Software Output Control Value
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH1SWCV : Channel 1 Software Output Control Value
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH2SWCV : Channel 2 Software Output Control Value
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH3SWCV : Channel 3 Software Output Control Value
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH4SWCV : Channel 4 Software Output Control Value
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH5SWCV : Channel 5 Software Output Control Value
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH6SWCV : Channel 6 Software Output Control Value
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH7SWCV : Channel 7 Software Output Control Value
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
Channel (n) Status And Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Match point direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Down count match
#1 : 1
Up count match
End of enumeration elements list.
ELSR0 : Edge or Level Select Register 0
bits : 2 - 2 (1 bit)
access : read-write
ELSR1 : Edge or Level Select Register 1
bits : 3 - 3 (1 bit)
access : read-write
MSR0 : Channel Mode Select Register 0
bits : 4 - 4 (1 bit)
access : read-write
MSR1 : Channel Mode Select Register 1
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHIF : Channel Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
Channel event has occurred.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.