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DMA0_CHANNEL0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :

Registers

STATUS

CONFIG

CHAN_LENGTH

MEM_START_ADDR

MEM_END_ADDR

PERIPH_ADDR

CHAN_ENABLE

DATA_TRANS_NUM

FIFO_LEFT_NUM

INTEN

RST

STOP


STATUS

Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINISH HALF_FINISH TRANS_ERROR

FINISH : transfer finished flag
bits : 0 - 0 (1 bit)
access : read-write

HALF_FINISH : transfer half finished flag
bits : 1 - 1 (1 bit)
access : read-write

TRANS_ERROR : transfer error flag
bits : 2 - 2 (1 bit)
access : read-write


CONFIG

DMA Config Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM2MEM CHAN_PRIORITY MEM_SIZE PERIPH_SIZE MEM_INCREMENT PERIPH_INCREMENT CHAN_CIRCULAR CHAN_DIR MEM_BYTE_MODE PERIPH_SEL

MEM2MEM : memory to memory transfer enable or disable
bits : 0 - 0 (1 bit)
access : read-write

CHAN_PRIORITY : channel priority select
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#0000 : LOW

DMA channel priority low

#0001 : MEDIUM

DMA channel priority medium

#0010 : HIGH

DMA channel priority high

#0011 : VERY_HIGH

DMA channel priority very high

End of enumeration elements list.

MEM_SIZE : memory size select
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

#0000 : 8BIT

MEM SIZE 8BIT

#0001 : 16BIT

MEM SIZE 16BIT

#0010 : 32BIT

MEM SIZE 32BIT

End of enumeration elements list.

PERIPH_SIZE : peripheral size select
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#0000 : 8BIT

PERIPH SIZE 8BIT

#0001 : 16BIT

PERIPH SIZE 16BIT

#0010 : 32BIT

PERIPH SIZE 32BIT

End of enumeration elements list.

MEM_INCREMENT : memory address increase or fix
bits : 7 - 7 (1 bit)
access : read-write

PERIPH_INCREMENT : peripheral address increase or fix
bits : 8 - 8 (1 bit)
access : read-write

CHAN_CIRCULAR : channel circular mode enable or disable
bits : 9 - 9 (1 bit)
access : read-write

CHAN_DIR : channel read data direction select
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0000 : READ_FROM_PERIPH

DMA read from peripheral

#0001 : READ_FROM_MEM

DMA read from memory

End of enumeration elements list.

MEM_BYTE_MODE : memory word segmentation transfer number
bits : 11 - 12 (2 bit)
access : read-write

PERIPH_SEL : peripheral select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : UART0_TX

UART0_TX as DMA peripheral

#0001 : UART0_RX

UART0_RX as DMA peripheral

#0010 : UART1_TX

UART1_TX as DMA peripheral

#0011 : UART1_RX

UART1_RX as DMA peripheral

#0100 : UART2_TX

UART2_TX as DMA peripheral

#0101 : UART2_RX

UART2_RX as DMA peripheral

#0110 : SPI0_TX

SPI0_TX as DMA peripheral

#0111 : SPI0_RX

SPI0_RX as DMA peripheral

#1000 : SPI1_TX

SPI1_TX as DMA peripheral

#1001 : SPI1_RX

SPI1_RX as DMA peripheral

#1010 : I2C0_TX

I2C0_TX as DMA peripheral

#1011 : I2C0_RX

I2C0_RX as DMA peripheral

#1100 : I2C1_TX

I2C1_TX as DMA peripheral

#1101 : I2C1_RX

I2C1_RX as DMA peripheral

#1110 : ADC0

ADC0 as DMA peripheral

End of enumeration elements list.


CHAN_LENGTH

Channel Length Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHAN_LENGTH CHAN_LENGTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHAN_LENGTH

CHAN_LENGTH : DMA channel transfer length
bits : 0 - 15 (16 bit)
access : read-write


MEM_START_ADDR

Memory Start Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_START_ADDR MEM_START_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_START_ADDR

MEM_START_ADDR : memory start address
bits : 0 - 31 (32 bit)
access : read-write


MEM_END_ADDR

Memory End Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_END_ADDR MEM_END_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_END_ADDR

MEM_END_ADDR : set memory end address
bits : 0 - 31 (32 bit)
access : read-write


PERIPH_ADDR

Peripheral Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIPH_ADDR PERIPH_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIPH_ADDR

PERIPH_ADDR : set peripheral address
bits : 0 - 31 (32 bit)
access : read-write


CHAN_ENABLE

Channel Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHAN_ENABLE CHAN_ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHAN_ENABLE

CHAN_ENABLE : channel enable
bits : 0 - 0 (1 bit)
access : read-write


DATA_TRANS_NUM

Data Transfer Number Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA_TRANS_NUM DATA_TRANS_NUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_TRANS_NUM

DATA_TRANS_NUM : data has been transfered number
bits : 0 - 15 (16 bit)
access : read-write


FIFO_LEFT_NUM

Internal FIFO Data Left Number Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_LEFT_NUM FIFO_LEFT_NUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_LEFT_NUM

FIFO_LEFT_NUM : internal fifo data left number
bits : 0 - 5 (6 bit)
access : read-write


INTEN

Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINISH_INTERRUPT_ENABLE HALF_FINISH_INTERRUPT_ENABLE TRANS_ERROR_INTERRUPT_ENABLE

FINISH_INTERRUPT_ENABLE : transfer finished interrupt enable or disable
bits : 0 - 0 (1 bit)
access : read-write

HALF_FINISH_INTERRUPT_ENABLE : transfer half finished interrupt enable or disable
bits : 1 - 1 (1 bit)
access : read-write

TRANS_ERROR_INTERRUPT_ENABLE : transfer error interrupt enable or disable
bits : 2 - 2 (1 bit)
access : read-write


RST

Reset Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RST RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WARM_RST HARD_RST FLUSH

WARM_RST : warm reset enable or disable
bits : 0 - 0 (1 bit)
access : read-write

HARD_RST : hard reset enable or disable
bits : 1 - 1 (1 bit)
access : read-write

FLUSH : dma flush enable or disable
bits : 2 - 2 (1 bit)
access : read-write


STOP

Stop Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STOP STOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP

STOP : DMA channel stop enable or disable
bits : 0 - 0 (1 bit)
access : read-write



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