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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL0

CHSEL0

CHSEL1

CHSEL2

CHSEL3

CHSEL4

CHSEL5

CHSEL6

CHSEL7

RESTART

DATAFMT

CTRL1

FIFODMACTRL

DATA

STATUS

CHSTATUS

INTEN

INTFL

SFRADDROFFSET

SFRADDR

SFRWRDATA

SFRRDDATA

SFRSTATUS

CLKCTRL

SAMPCLKCTRL


CTRL0

Control Register 0.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_EN BIAS_EN SKIP_CAL CHOP_FORCE RESETB

ADC_EN : ADC Enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : dis

Disable ADC.

1 : en

enable ADC.

End of enumeration elements list.

BIAS_EN : Bias Enable.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : dis

Disable Bias.

1 : en

Enable Bias.

End of enumeration elements list.

SKIP_CAL : Skip Calibration Enable.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : no_skip

Do not skip calibration.

1 : skip

Skip calibration.

End of enumeration elements list.

CHOP_FORCE : Chop Force Control.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : dis

Do not force chop mode.

1 : en

Force chop Mode.

End of enumeration elements list.

RESETB : Reset ADC.
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : reset

reset ADC.

1 : activate

activate ADC.

End of enumeration elements list.


CHSEL0

Channel Select Register 0.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSEL0 CHSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slot0_id slot1_id slot2_id slot3_id

slot0_id : channel assignment for slot 0.
bits : 0 - 4 (5 bit)
access : read-write

slot1_id : channel assignment for slot 1.
bits : 8 - 20 (13 bit)
access : read-write

slot2_id : channel assignment for slot 2.
bits : 16 - 36 (21 bit)
access : read-write

slot3_id : channel assignment for slot 3.
bits : 24 - 52 (29 bit)
access : read-write


CHSEL1

Channel Select Register 1.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSEL1 CHSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slot4_id slot5_id slot6_id slot7_id

slot4_id : channel assignment for slot 4.
bits : 0 - 4 (5 bit)
access : read-write

slot5_id : channel assignment for slot 5.
bits : 8 - 20 (13 bit)
access : read-write

slot6_id : channel assignment for slot 6.
bits : 16 - 36 (21 bit)
access : read-write

slot7_id : channel assignment for slot 7.
bits : 24 - 52 (29 bit)
access : read-write


CHSEL2

Channel Select Register 2.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSEL2 CHSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slot8_id slot9_id slot10_id slot11_id

slot8_id : channel assignment for slot 8.
bits : 0 - 4 (5 bit)
access : read-write

slot9_id : channel assignment for slot 9.
bits : 8 - 20 (13 bit)
access : read-write

slot10_id : channel assignment for slot 10.
bits : 16 - 36 (21 bit)
access : read-write

slot11_id : channel assignment for slot 11.
bits : 24 - 52 (29 bit)
access : read-write


CHSEL3

Channel Select Register 3.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSEL3 CHSEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slot12_id slot13_id slot14_id slot15_id

slot12_id : channel assignment for slot 12.
bits : 0 - 4 (5 bit)
access : read-write

slot13_id : channel assignment for slot 13.
bits : 8 - 20 (13 bit)
access : read-write

slot14_id : channel assignment for slot 14.
bits : 16 - 36 (21 bit)
access : read-write

slot15_id : channel assignment for slot 15.
bits : 24 - 52 (29 bit)
access : read-write


CHSEL4

Channel Select Register 4.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSEL4 CHSEL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slot16_id slot17_id slot18_id slot19_id

slot16_id : channel assignment for slot 16.
bits : 0 - 4 (5 bit)
access : read-write

slot17_id : channel assignment for slot 17.
bits : 8 - 20 (13 bit)
access : read-write

slot18_id : channel assignment for slot 18.
bits : 16 - 36 (21 bit)
access : read-write

slot19_id : channel assignment for slot 19.
bits : 24 - 52 (29 bit)
access : read-write


CHSEL5

Channel Select Register 5.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSEL5 CHSEL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slot20_id slot21_id slot22_id slot23_id

slot20_id : channel assignment for slot 20.
bits : 0 - 4 (5 bit)
access : read-write

slot21_id : channel assignment for slot 21.
bits : 8 - 20 (13 bit)
access : read-write

slot22_id : channel assignment for slot 22.
bits : 16 - 36 (21 bit)
access : read-write

slot23_id : channel assignment for slot 23.
bits : 24 - 52 (29 bit)
access : read-write


CHSEL6

Channel Select Register 6.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSEL6 CHSEL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slot24_id slot25_id slot26_id slot27_id

slot24_id : channel assignment for slot 24.
bits : 0 - 4 (5 bit)
access : read-write

slot25_id : channel assignment for slot 25.
bits : 8 - 20 (13 bit)
access : read-write

slot26_id : channel assignment for slot 26.
bits : 16 - 36 (21 bit)
access : read-write

slot27_id : channel assignment for slot 27.
bits : 24 - 52 (29 bit)
access : read-write


CHSEL7

Channel Select Register 7.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSEL7 CHSEL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 slot28_id slot29_id slot30_id slot31_id

slot28_id : channel assignment for slot 28.
bits : 0 - 4 (5 bit)
access : read-write

slot29_id : channel assignment for slot 29.
bits : 8 - 20 (13 bit)
access : read-write

slot30_id : channel assignment for slot 30.
bits : 16 - 36 (21 bit)
access : read-write

slot31_id : channel assignment for slot 31.
bits : 24 - 52 (29 bit)
access : read-write


RESTART

Restart Count Control Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESTART RESTART read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Number of sample periods to skip before restarting a continuous mode sequence
bits : 0 - 15 (16 bit)
access : read-write


DATAFMT

Channel Data Format Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAFMT DATAFMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE

MODE : Data format control
bits : 0 - 31 (32 bit)
access : read-write


CTRL1

Control Register 1.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START TRIG_MODE CNV_MODE SAMP_CK_OFF TRIG_SEL TS_SEL AVG NUM_SLOTS

START : Start conversion control.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : stop

Stop conversions.

1 : start

Start conversions.

End of enumeration elements list.

TRIG_MODE : Trigger mode control.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : software

software trigger mode.

1 : hardware

hardware trigger mode.

End of enumeration elements list.

CNV_MODE : Conversion mode control.
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : atomic

Do one conversion sequence.

1 : continuous

Do continuous conversion sequences.

End of enumeration elements list.

SAMP_CK_OFF : Sample clock off control.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : always

Sample clock always generated.

1 : cnv_only

Sample clock generated only when converting.

End of enumeration elements list.

TRIG_SEL : Hardware trigger source select.
bits : 4 - 10 (7 bit)
access : read-write

TS_SEL : Temp sensor select.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : dis

Temp sensor is not one of the slots in the sequence.

1 : en

Temp sensor is one of the slots in the sequence.

End of enumeration elements list.

AVG : Number of samples to average for each output data code.
bits : 8 - 18 (11 bit)
access : read-write

Enumeration:

0 : avg1

1 Sample per output code.

1 : avg2

2 Samples per output code.

2 : avg4

4 Samples per output code.

3 : avg8

8 Samples per output code.

4 : avg16

16 Samples per output code.

5 : avg32

32 Samples per output code.

End of enumeration elements list.

NUM_SLOTS : Number of slots enabled for the conversion sequence
bits : 16 - 36 (21 bit)
access : read-write


FIFODMACTRL

FIFO and DMA control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFODMACTRL FIFODMACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_EN FLUSH DATA_FORMAT THRESH

DMA_EN : DMA Enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : dis

Disable DMA.

1 : en

Enable DMA.

End of enumeration elements list.

FLUSH : FIFO Flush.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : normal

Normal FIFO operation.

1 : flush

Flush FIFO.

End of enumeration elements list.

DATA_FORMAT : DATA format control.
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : data_status

Data and Status in FIFO.

1 : data_only

Only Data in FIFO.

2 : raw_data_only

Only Raw Data in FIFO.

End of enumeration elements list.

THRESH : FIFO Threshold. These bits define the FIFO interrupt threshold.
bits : 8 - 23 (16 bit)
access : read-write


DATA

Data Register (FIFO).
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA CHAN INVALID CLIPPED

DATA : Conversion data.
bits : 0 - 15 (16 bit)
access : read-only

CHAN : Channel for the data.
bits : 16 - 36 (21 bit)
access : read-only

INVALID : Invalid status for the data.
bits : 24 - 48 (25 bit)
access : read-only

CLIPPED : Clipped status for the data.
bits : 31 - 62 (32 bit)
access : read-only


STATUS

Status Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY EMPTY FULL FIFO_LEVEL

READY : Indication that the ADC is in ON power state
bits : 0 - 0 (1 bit)
access : read-only

EMPTY : FIFO Empty
bits : 1 - 2 (2 bit)
access : read-only

FULL : FIFO full
bits : 2 - 4 (3 bit)
access : read-only

FIFO_LEVEL : Number of entries in FIFO available to read
bits : 8 - 23 (16 bit)
access : read-only


CHSTATUS

Channel Status
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLIPPED

CLIPPED :
bits : 0 - 31 (32 bit)
access : read-write


INTEN

Interrupt Enable Register.
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY ABORT START_DET SEQ_STARTED SEQ_DONE CONV_DONE CLIPPED FIFO_LVL FIFO_UFL FIFO_OFL

READY : ADC is ready.
bits : 0 - 0 (1 bit)
access : read-write

ABORT : Conversion start is aborted.
bits : 2 - 4 (3 bit)
access : read-write

START_DET : Conversion start is detected.
bits : 3 - 6 (4 bit)
access : read-write

SEQ_STARTED :
bits : 4 - 8 (5 bit)
access : read-write

SEQ_DONE :
bits : 5 - 10 (6 bit)
access : read-write

CONV_DONE :
bits : 6 - 12 (7 bit)
access : read-write

CLIPPED :
bits : 7 - 14 (8 bit)
access : read-write

FIFO_LVL :
bits : 8 - 16 (9 bit)
access : read-write

FIFO_UFL :
bits : 9 - 18 (10 bit)
access : read-write

FIFO_OFL :
bits : 10 - 20 (11 bit)
access : read-write


INTFL

Interrupt Flags Register.
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFL INTFL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READY ABORT START_DET SEQ_STARTED SEQ_DONE CONV_DONE CLIPPED FIFO_LVL FIFO_UFL FIFO_OFL

READY : ADC is ready.
bits : 0 - 0 (1 bit)
access : read-write

ABORT : Conversion start is aborted.
bits : 2 - 4 (3 bit)
access : read-write

START_DET : Conversion start is detected.
bits : 3 - 6 (4 bit)
access : read-write

SEQ_STARTED :
bits : 4 - 8 (5 bit)
access : read-write

SEQ_DONE :
bits : 5 - 10 (6 bit)
access : read-write

CONV_DONE :
bits : 6 - 12 (7 bit)
access : read-write

CLIPPED :
bits : 7 - 14 (8 bit)
access : read-write

FIFO_LVL :
bits : 8 - 16 (9 bit)
access : read-write

FIFO_UFL :
bits : 9 - 18 (10 bit)
access : read-write

FIFO_OFL :
bits : 10 - 20 (11 bit)
access : read-write


SFRADDROFFSET

SFR Address Offset Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFRADDROFFSET SFRADDROFFSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : Address Offset for SAR Digital
bits : 0 - 7 (8 bit)
access : read-write


SFRADDR

SFR Address Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFRADDR SFRADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Address to SAR Digital
bits : 0 - 7 (8 bit)
access : read-write


SFRWRDATA

SFR Write Data Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFRWRDATA SFRWRDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA to SAR Digital
bits : 0 - 7 (8 bit)
access : read-write


SFRRDDATA

SFR Read Data Register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFRRDDATA SFRRDDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA from SAR Digital
bits : 0 - 7 (8 bit)
access : read-only


SFRSTATUS

SFR Status Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFRSTATUS SFRSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NACK

NACK : NACK status for SAR Digital SFR communication
bits : 0 - 0 (1 bit)
access : read-only


CLKCTRL

Clock Control Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCTRL CLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL CLKDIV

CLKSEL : Clock source select.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : HCLK

Select HCLK.

1 : CLK_ADC0

Select CLK_ADC0.

2 : CLK_ADC1

Select CLK_ADC1.

3 : CLK_ADC2

Select CLK_ADC2.

End of enumeration elements list.

CLKDIV : Clock divider control.
bits : 4 - 10 (7 bit)
access : read-write

Enumeration:

0 : DIV2

Divide by 2.

1 : DIV4

Divide by 4.

2 : DIV8

Divide by 8.

3 : DIV16

Divide by 16.

4 : DIV1

Divide by 1.

End of enumeration elements list.


SAMPCLKCTRL

Sample Clock Control Register.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPCLKCTRL SAMPCLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRACK_CNT IDLE_CNT

TRACK_CNT : Number of cycles for SAMPLE_CLK high time.
bits : 0 - 7 (8 bit)
access : read-write

IDLE_CNT : Number of cycles for SAMPLE_CLK low time.
bits : 16 - 47 (32 bit)
access : read-write



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