CTRL

DMA_SRC

SCA_CTRL0

SCA_CTRL1

SCA_STAT

SCA_PPX_ADDR

SCA_PPY_ADDR

SCA_PPZ_ADDR

SCA_PQX_ADDR

SCA_PQY_ADDR

SCA_PQZ_ADDR

SCA_RDSA_ADDR

SCA_RES_ADDR

SCA_OP_BUFF_ADDR

SCA_MODDATA

SCA_NRNG

DMA_DEST

DMA_CNT

DIN0

DIN1

DIN2

DIN3

DOUT0

DOUT1

DOUT2

DOUT3

CIPHER_CTRL

CRC_POLY

CRC_VAL

HAM_ECC

CIPHER_INIT0

CIPHER_INIT1

CIPHER_INIT2

CIPHER_INIT3

CIPHER_KEY0

CIPHER_KEY1

CIPHER_KEY2

CIPHER_KEY3

CIPHER_KEY4

CIPHER_KEY5

CIPHER_KEY6

CIPHER_KEY7

HASH_CTRL

HASH_DIGEST0

HASH_DIGEST1

HASH_DIGEST2

HASH_DIGEST3

HASH_DIGEST4

HASH_DIGEST5

HASH_DIGEST6

HASH_DIGEST7

HASH_DIGEST8

HASH_DIGEST9

HASH_DIGEST10

HASH_DIGEST11

HASH_DIGEST12

HASH_DIGEST13

HASH_DIGEST14

HASH_DIGEST15

CRC_CTRL

HASH_MSG_SZ0

HASH_MSG_SZ1

HASH_MSG_SZ2

HASH_MSG_SZ3

AAD_LENGTH_0

AAD_LENGTH_1

PLD_LENGTH_0

PLD_LENGTH_1

TAGMIC0

TAGMIC1

TAGMIC2

TAGMIC3

RST : Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle.
bits : 0 - 0 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

INTR : Interrupt Enable. Generates an interrupt when done or error set.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

SRC : Source Select. This bit selects the hash function and CRC generator input source.
bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

BSO : Byte Swap Output. Note. No byte swap will occur if there is not a full word.
bits : 4 - 4 (1 bit)

BSI : Byte Swap Input. Note. No byte swap will occur if there is not a full word.
bits : 5 - 5 (1 bit)

WAIT_EN : Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready.
bits : 6 - 6 (1 bit)

WAIT_POL : Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state.
bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

WRSRC : Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled.
bits : 8 - 9 (2 bit)

Enumeration:

End of enumeration elements list.

RDSRC : Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator.
bits : 10 - 11 (2 bit)

Enumeration:

End of enumeration elements list.

FLAG_MODE : Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs.
bits : 14 - 14 (1 bit)

Enumeration:

End of enumeration elements list.

DMADNEMSK : DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA.
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

DMA_DONE : DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation.
bits : 24 - 24 (1 bit)

Enumeration:

End of enumeration elements list.

GLS_DONE : Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator.
bits : 25 - 25 (1 bit)

HSH_DONE : Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation.
bits : 26 - 26 (1 bit)

CPH_DONE : Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation.
bits : 27 - 27 (1 bit)

ERR : AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block.
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDY : Ready. Crypto block ready for more data.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DONE : Done. One or more cryptographic calculations complete (logical OR of done flags).
bits : 31 - 31 (1 bit)
access : read-only

ADDR : DMA Source Address.
bits : 0 - 31 (32 bit)

STC : Start Calculation.
bits : 0 - 0 (1 bit)

SCAIE : SCA Interrupt Enable.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

ABORT : Abort Operation.
bits : 2 - 2 (1 bit)

ERMEM : Erase Cryptographic Memory.
bits : 4 - 4 (1 bit)

MANPARAM : ECC Parameter Source.
bits : 5 - 5 (1 bit)

HWKEY : Hardware Key Select.
bits : 6 - 6 (1 bit)

OPCODE : SCA Opcode.
bits : 8 - 12 (5 bit)

MODADDR : MODULO Address Offset.
bits : 16 - 20 (5 bit)

ECCSIZE : ECC Size.
bits : 24 - 25 (2 bit)

MAN : SCA Mode.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

AUTOCARRY : Automatically propagate the carry for the next operation.
bits : 1 - 1 (1 bit)

PLUSONE : Enable Carry propagation for the next operation.
bits : 2 - 2 (1 bit)

NRNG : NRNG.
bits : 5 - 5 (1 bit)

CARRYPOS : To set Carry location.
bits : 8 - 17 (10 bit)

BUSY : SCA Busy.
bits : 0 - 0 (1 bit)

SCAIF : SCA Interrupt Flag.
bits : 1 - 1 (1 bit)

PVF1 : Point 1 Verification Failed.
bits : 2 - 2 (1 bit)

PVF2 : Point 2 Verification Failed.
bits : 3 - 3 (1 bit)

FSMERR : FSM Transition Error.
bits : 4 - 4 (1 bit)

COMPERR : EC Computation Error.
bits : 5 - 5 (1 bit)

MEMERR : SCA Memory Access Error.
bits : 6 - 6 (1 bit)

CARRY : Carry on ongoing operation.
bits : 8 - 8 (1 bit)

GTE2I2 : Modulo 2x Result.
bits : 9 - 9 (1 bit)

ALUNEG1 : ALU 2 SubSign of the subtraction result for ALU_2.
bits : 10 - 10 (1 bit)

ALUNEG2 : ALU 2 SubSign of the subtraction result for ALU_2.
bits : 11 - 11 (1 bit)

ADDR : Point P Coordinate Data Pointer.
bits : 0 - 31 (32 bit)

ADDR : Point P Coordinate Data Pointer.
bits : 0 - 31 (32 bit)

ADDR : Point P Coordinate Data Pointer.
bits : 0 - 31 (32 bit)

ADDR : Point Q Coordinate Data Pointer.
bits : 0 - 31 (32 bit)

ADDR : Point Q Coordinate Data Pointer.
bits : 0 - 31 (32 bit)

ADDR : Point Q Coordinate Data Pointer.
bits : 0 - 31 (32 bit)

ADDR : The starting address of the R portion for R, S ECDSA signature.
bits : 0 - 31 (32 bit)

ADDR : Starting address of result storage.
bits : 0 - 31 (32 bit)

ADDR : Starting address of operation buffer.
bits : 0 - 31 (32 bit)

DATA : Used to load the SCA modulo for modular operations.
bits : 0 - 31 (32 bit)

ADDR : DMA Destination Address.
bits : 0 - 31 (32 bit)

ADDR : DMA Byte Address.
bits : 0 - 31 (32 bit)

DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)

DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)

DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)

DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)

DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)

DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)

DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)

DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)

ENC : Encrypt. Select encryption or decryption of input data.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

KEY : Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

SRC : Source of Random key.
bits : 2 - 3 (2 bit)

Enumeration:

End of enumeration elements list.

CIPHER : Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation.
bits : 4 - 6 (3 bit)

Enumeration:

End of enumeration elements list.

MODE : Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes.
bits : 8 - 10 (3 bit)

Enumeration:

End of enumeration elements list.

HVC : H Vector Computation.
bits : 11 - 11 (1 bit)
access : read-only

DTYPE : GCM/CCM data type.
bits : 12 - 12 (1 bit)
access : read-only

CCMM : CCM M Parameter.
bits : 13 - 15 (3 bit)
access : read-only

CCML : CCM L Parameter.
bits : 16 - 18 (3 bit)
access : read-only

POLY : CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.
bits : 0 - 31 (32 bit)

VAL : CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit.
bits : 0 - 31 (32 bit)

ECC : Hamming ECC Value. These bits are the even parity of their corresponding bit groups.
bits : 0 - 15 (16 bit)

PAR : Parity. This is the parity of the entire array.
bits : 16 - 16 (1 bit)

Enumeration:

End of enumeration elements list.

IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)

IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)

IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)

IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)

KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)

KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)

KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)

KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)

KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)

KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)

KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)

KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)

INIT : Initialize. Initializes hash registers with standard constants.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

XOR : XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

HASH : Hash function selection.
bits : 2 - 4 (3 bit)

Enumeration:

End of enumeration elements list.

LAST : Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash.
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)