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AES

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

FIFO

STATUS

INTFL

INTEN


CTRL

AES Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DMA_RX_EN DMA_TX_EN START INPUT_FLUSH OUTPUT_FLUSH KEY_SIZE TYPE

EN : AES Enable
bits : 0 - 0 (1 bit)
access : read-write

DMA_RX_EN : DMA Request To Read Data Output FIFO
bits : 1 - 2 (2 bit)
access : read-write

DMA_TX_EN : DMA Request To Write Data Input FIFO
bits : 2 - 4 (3 bit)
access : read-write

START : Start AES Calculation
bits : 3 - 6 (4 bit)
access : read-write

INPUT_FLUSH : Flush the data input FIFO
bits : 4 - 8 (5 bit)
access : read-write

OUTPUT_FLUSH : Flush the data output FIFO
bits : 5 - 10 (6 bit)
access : read-write

KEY_SIZE : Encryption Key Size
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

0 : AES128

128 Bits.

1 : AES192

192 Bits.

2 : AES256

256 Bits.

End of enumeration elements list.

TYPE : Encryption Type Selection
bits : 8 - 17 (10 bit)
access : read-write


FIFO

AES Data Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : AES FIFO
bits : 0 - 0 (1 bit)
access : read-write


STATUS

AES Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY INPUT_EM INPUT_FULL OUTPUT_EM OUTPUT_FULL

BUSY : AES Busy Status
bits : 0 - 0 (1 bit)
access : read-write

INPUT_EM : Data input FIFO empty status
bits : 1 - 2 (2 bit)
access : read-write

INPUT_FULL : Data input FIFO full status
bits : 2 - 4 (3 bit)
access : read-write

OUTPUT_EM : Data output FIFO empty status
bits : 3 - 6 (4 bit)
access : read-write

OUTPUT_FULL : Data output FIFO full status
bits : 4 - 8 (5 bit)
access : read-write


INTFL

AES Interrupt Flag Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFL INTFL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE KEY_CHANGE KEY_ZERO OV KEY_ONE

DONE : AES Done Interrupt
bits : 0 - 0 (1 bit)
access : read-write

KEY_CHANGE : External AES Key Changed Interrupt
bits : 1 - 2 (2 bit)
access : read-write

KEY_ZERO : External AES Key Zero Interrupt
bits : 2 - 4 (3 bit)
access : read-write

OV : Data Output FIFO Overrun Interrupt
bits : 3 - 6 (4 bit)
access : read-write

KEY_ONE : KEY_ONE
bits : 4 - 8 (5 bit)
access : read-write


INTEN

AES Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE KEY_CHANGE KEY_ZERO OV KEY_ONE

DONE : AES Done Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

KEY_CHANGE : External AES Key Changed Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

KEY_ZERO : External AES Key Zero Interrupt Enable
bits : 2 - 4 (3 bit)
access : read-write

OV : Data Output FIFO Overrun Interrupt Enable
bits : 3 - 6 (4 bit)
access : read-write

KEY_ONE : KEY_ONE
bits : 4 - 8 (5 bit)
access : read-write



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