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MCR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

LPPIOCTRL

PCLKDIS

AESKEY

ADC_CFG0

ADC_CFG1

RST

ADC_CFG2

CLKCTRL

AINCOMP


LPPIOCTRL

Low Power Peripheral IO Control Register.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPPIOCTRL LPPIOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMR0_I LPTMR0_O LPTMR1_I LPTMR1_O LPUART0_RX LPUART0_TX LPUART0_CTS LPUART0_RTS

LPTMR0_I : Enable control for LPTMR0 input.
bits : 0 - 0 (1 bit)

LPTMR0_O : Enable control for LPTMR0 output.
bits : 1 - 1 (1 bit)

LPTMR1_I : Enable control for LPTMR1 input.
bits : 2 - 2 (1 bit)

LPTMR1_O : Enable control for LPTMR1 output.
bits : 3 - 3 (1 bit)

LPUART0_RX : Enable control for LPUART0 RX.
bits : 4 - 4 (1 bit)

LPUART0_TX : Enable control for LPUART0 TX.
bits : 5 - 5 (1 bit)

LPUART0_CTS : Enable control for LPUART0 CTS.
bits : 6 - 6 (1 bit)

LPUART0_RTS : Enable control for LPUART0 RTS.
bits : 7 - 7 (1 bit)


PCLKDIS

Low Power Peripheral Clock Disable.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLKDIS PCLKDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMR0 LPTMR1 LPUART0

LPTMR0 : Low Power Timer0 Clock Disable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : en

enable it.

1 : dis

disable it.

End of enumeration elements list.

LPTMR1 : Low Power Timer1 Clock Disable.
bits : 1 - 1 (1 bit)

LPUART0 : Low Power UART0 Clock Disable.
bits : 2 - 2 (1 bit)


AESKEY

AES Key Pointer and Status.
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AESKEY AESKEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR

PTR : AESKEY Pointer and Status.
bits : 0 - 15 (16 bit)


ADC_CFG0

ADC Cfig Register0.
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFG0 ADC_CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LP_5K_DIS LP_50K_DIS EXT_REF REF_SEL

LP_5K_DIS : Disable 5K divider option in low power modes
bits : 0 - 0 (1 bit)

Enumeration:

0 : en

Enable.

1 : dis

Disable.

End of enumeration elements list.

LP_50K_DIS : Disable 50K divider option in low power modes
bits : 1 - 1 (1 bit)

Enumeration:

0 : EN

Enable.

1 : DIS

Disable.

End of enumeration elements list.

EXT_REF : External Reference
bits : 2 - 2 (1 bit)

REF_SEL : Reference Select
bits : 3 - 3 (1 bit)


ADC_CFG1

ADC Config Register1.
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFG1 ADC_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_PU_DYN CH1_PU_DYN CH2_PU_DYN CH3_PU_DYN CH4_PU_DYN CH5_PU_DYN CH6_PU_DYN CH7_PU_DYN CH8_PU_DYN CH9_PU_DYN CH10_PU_DYN CH11_PU_DYN CH12_PU_DYN

CH0_PU_DYN : ADC PU Dynamic Control for CH0
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

divider select always used.

1 : en

divider select only used when channel is selected.

End of enumeration elements list.

CH1_PU_DYN : ADC PU Dynamic Control for CH1
bits : 1 - 1 (1 bit)

CH2_PU_DYN : ADC PU Dynamic Control for CH2
bits : 2 - 2 (1 bit)

CH3_PU_DYN : ADC PU Dynamic Control for CH3
bits : 3 - 3 (1 bit)

CH4_PU_DYN : ADC PU Dynamic Control for CH4
bits : 4 - 4 (1 bit)

CH5_PU_DYN : ADC PU Dynamic Control for CH5
bits : 5 - 5 (1 bit)

CH6_PU_DYN : ADC PU Dynamic Control for CH6
bits : 6 - 6 (1 bit)

CH7_PU_DYN : ADC PU Dynamic Control for CH7
bits : 7 - 7 (1 bit)

CH8_PU_DYN : ADC PU Dynamic Control for CH8
bits : 8 - 8 (1 bit)

CH9_PU_DYN : ADC PU Dynamic Control for CH9
bits : 9 - 9 (1 bit)

CH10_PU_DYN : ADC PU Dynamic Control for CH10
bits : 10 - 10 (1 bit)

CH11_PU_DYN : ADC PU Dynamic Control for CH11
bits : 11 - 11 (1 bit)

CH12_PU_DYN : ADC PU Dynamic Control for CH12
bits : 12 - 12 (1 bit)


RST

Low Power Reset Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RST RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMR0 LPTMR1 LPUART0

LPTMR0 : Low Power Timer0 Reset.
bits : 0 - 0 (1 bit)

Enumeration: reset ( read-write )

0 : reset_done

Reset complete.

1 : busy

Starts Reset or indicates reset in progress.

End of enumeration elements list.

LPTMR1 : Low Power Timer1 Reset.
bits : 1 - 1 (1 bit)

LPUART0 : Low Power UART0 Reset.
bits : 2 - 2 (1 bit)


ADC_CFG2

ADC Config Register2.
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CFG2 ADC_CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12

CH0 : Divider Select for channel 0
bits : 0 - 1 (2 bit)

Enumeration:

0 : div1

Pass through, no divider.

1 : div2_5k

Divide by 2, 5Kohm.

2 : div2_50k

Divide by 2, 50Kohm.

End of enumeration elements list.

CH1 : Divider Select for channel 1
bits : 2 - 3 (2 bit)

CH2 : Divider Select for channel 2
bits : 4 - 5 (2 bit)

CH3 : Divider Select for channel 3
bits : 6 - 7 (2 bit)

CH4 : Divider Select for channel 4
bits : 8 - 9 (2 bit)

CH5 : Divider Select for channel 5
bits : 10 - 11 (2 bit)

CH6 : Divider Select for channel 6
bits : 12 - 13 (2 bit)

CH7 : Divider Select for channel 7
bits : 14 - 15 (2 bit)

CH8 : Divider Select for channel 8
bits : 16 - 17 (2 bit)

CH9 : Divider Select for channel 9
bits : 18 - 19 (2 bit)

CH10 : Divider Select for channel 10
bits : 20 - 21 (2 bit)

CH11 : Divider Select for channel 11
bits : 22 - 23 (2 bit)

CH12 : Divider Select for channel 12
bits : 24 - 25 (2 bit)


CLKCTRL

Clock Control.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCTRL CLKCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERTCO_PD ERTCO_EN

ERTCO_PD : 32KHz Crystal Oscillator Power Down.
bits : 16 - 16 (1 bit)

ERTCO_EN : 32KHz Crystal Oscillator Enable.
bits : 17 - 17 (1 bit)

Enumeration:

0 : dis

Is Disabled.

1 : en

Is Enabled.

End of enumeration elements list.


AINCOMP

AIN Comparator.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AINCOMP AINCOMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD HYST NSEL_COMP0 PSEL_COMP0 NSEL_COMP1 PSEL_COMP1

PD : AIN Comparator Power Down control.
bits : 0 - 1 (2 bit)

HYST : AIN Comparator Hysteresis control.
bits : 2 - 3 (2 bit)

NSEL_COMP0 : Negative input select for AIN Comparator 0.
bits : 16 - 19 (4 bit)

PSEL_COMP0 : Positive input select for AIN Comparator 0
bits : 20 - 23 (4 bit)

NSEL_COMP1 : Negative input select for AIN Comparator 1
bits : 24 - 27 (4 bit)

PSEL_COMP1 : Positive input select for AIN Comparator 1
bits : 28 - 31 (4 bit)



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