Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
DMA Control Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 Interrupt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CH1 : Channel 1 Interrupt Enable.
bits : 1 - 1 (1 bit)
CH2 : Channel 2 Interrupt Enable.
bits : 2 - 2 (1 bit)
CH3 : Channel 3 Interrupt Enable.
bits : 3 - 3 (1 bit)
CH4 : Channel 4 Interrupt Enable.
bits : 4 - 4 (1 bit)
CH5 : Channel 5 Interrupt Enable.
bits : 5 - 5 (1 bit)
CH6 : Channel 6 Interrupt Enable.
bits : 6 - 6 (1 bit)
CH7 : Channel 7 Interrupt Enable.
bits : 7 - 7 (1 bit)
DMA Channel Control Register.
address_offset : 0x100 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQUEST : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
ADC
0x0A : I2C2RX
I2C2 RX
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : AESRX
AES RX
0x1C : UART3RX
UART3 RX
0x1E : I2SRX
I2S RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2A : I2C2TX
I2C2 TX
0x2C : CRCTX
CRC TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : AESTX
AES TX
0x3C : UART3TX
UART3 TX
0x3E : I2STX
I2S TX
End of enumeration elements list.
TO_WAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TO_PER : Timeout Period Select.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
TO_CLKDIV : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BURST_SIZE : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
DIS_IE : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZ_IE : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x104 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATUS : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_IF : Count-to-Zero (CTZ) Interrupt Flag
bits : 2 - 2 (1 bit)
RLD_IF : Reload Event Interrupt Flag.
bits : 3 - 3 (1 bit)
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
TO_IF : Time-Out Event Interrupt Flag.
bits : 6 - 6 (1 bit)
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x108 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x10C Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x110 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x114 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x118 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x11C Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
EN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Interrupt Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.
bits : 0 - 0 (1 bit)
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CH1 :
bits : 1 - 1 (1 bit)
CH2 :
bits : 2 - 2 (1 bit)
CH3 :
bits : 3 - 3 (1 bit)
CH4 :
bits : 4 - 4 (1 bit)
CH5 :
bits : 5 - 5 (1 bit)
CH6 :
bits : 6 - 6 (1 bit)
CH7 :
bits : 7 - 7 (1 bit)
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