\n

FLC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ADDR

INTR

ECCDATA

DATA

CLKDIV

ACTRL

CTRL

WELR0

WELR1

RLR0

RLR1


ADDR

Flash Write Address.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Address for next operation.
bits : 0 - 31 (32 bit)


INTR

Flash Interrupt Register.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE AF DONEIE AFIE

DONE : Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.
bits : 0 - 0 (1 bit)

Enumeration:

0 : inactive

No interrupt is pending.

1 : pending

An interrupt is pending.

End of enumeration elements list.

AF : Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.
bits : 1 - 1 (1 bit)

Enumeration:

0 : noError

No Failure.

1 : error

Failure occurs.

End of enumeration elements list.

DONEIE : Flash Done Interrupt Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : disable

Disable.

1 : enable

Enable.

End of enumeration elements list.

AFIE :
bits : 9 - 9 (1 bit)


ECCDATA

ECC Data Register.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCDATA ECCDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVEN ODD

EVEN : Error Correction Code Odd Data.
bits : 0 - 8 (9 bit)

ODD : Error Correction Code Even Data.
bits : 16 - 24 (9 bit)


DATA

Flash Write Data.
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data next operation.
bits : 0 - 31 (32 bit)


CLKDIV

Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV

CLKDIV : Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.
bits : 0 - 7 (8 bit)


ACTRL

Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3 pflc-actrl = 0xa1e34f20 pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ACTRL ACTRL write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTRL

ACTRL : Access control.
bits : 0 - 31 (32 bit)


CTRL

Flash Control Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR ME PGE ERASE_CODE PEND LVE UNLOCK

WR : Write. This bit is automatically cleared after the operation.
bits : 0 - 0 (1 bit)

Enumeration:

0 : complete

No operation/complete.

1 : start

Start operation.

End of enumeration elements list.

ME : Mass Erase. This bit is automatically cleared after the operation.
bits : 1 - 1 (1 bit)

PGE : Page Erase. This bit is automatically cleared after the operation.
bits : 2 - 2 (1 bit)

ERASE_CODE : Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.
bits : 8 - 15 (8 bit)

Enumeration:

0 : nop

No operation.

0x55 : erasePage

Enable Page Erase.

0xAA : eraseAll

Enable Mass Erase. The debug port must be enabled.

End of enumeration elements list.

PEND : Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

0 : idle

Idle.

1 : busy

Busy.

End of enumeration elements list.

LVE : Low Voltage enable.
bits : 25 - 25 (1 bit)

UNLOCK : Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.
bits : 28 - 31 (4 bit)

Enumeration:

2 : unlocked

Flash Unlocked.

3 : locked

Flash Locked.

End of enumeration elements list.


WELR0

WELR0
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WELR0 WELR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WELR0

WELR0 : Access control.
bits : 0 - 31 (32 bit)


WELR1

WELR1
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WELR1 WELR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WELR1

WELR1 : Access control.
bits : 0 - 31 (32 bit)


RLR0

RLR0
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RLR0 RLR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLR0

RLR0 : Access control.
bits : 0 - 31 (32 bit)


RLR1

RLR1
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RLR1 RLR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RLR1

RLR1 : Access control.
bits : 0 - 31 (32 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.