SYSCTRL

PCLKDIV

PCLKDIS0

MEMCTRL

MEMZ

RST0

SYSST

RST1

PCLKDIS1

EVENTEN

REVISION

SYSIE

ECCERR

ECCCED

ECCIE

ECCADDR

CLKCTRL

PM

SBUSARB : System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.
bits : 1 - 2 (2 bit)

Enumeration:

End of enumeration elements list.

FLASH_PAGE_FLIP : .
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

FPU_DIS : Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

ICC0_FLUSH : Internal Cache Controller Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4.
bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

CCHK : Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.
bits : 13 - 13 (1 bit)

Enumeration:

End of enumeration elements list.

SWD_DIS : Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)
bits : 14 - 14 (1 bit)

Enumeration:

End of enumeration elements list.

CHKRES : ROM Checksum Result. This bit is only valid when CHKRD=1.
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

AON_CLKDIV : Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider
bits : 0 - 2 (3 bit)

Enumeration:

End of enumeration elements list.

DIV_CLK_OUT_CTRL : DIV_CLK_OUT Control
bits : 14 - 15 (2 bit)

Enumeration:

End of enumeration elements list.

DIV_CLK_OUT_EN : DIV_CLK_OUT Enable
bits : 16 - 16 (1 bit)

Enumeration:

End of enumeration elements list.

GPIO0 : GPIO0 Disable.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

GPIO1 : GPIO1 Disable.
bits : 1 - 1 (1 bit)

DMA : DMA Disable.
bits : 5 - 5 (1 bit)

SPI0 : SPI 0 Disable.
bits : 6 - 6 (1 bit)

SPI1 : SPI 1 Disable.
bits : 7 - 7 (1 bit)

SPI2 : SPI 2 Disable.
bits : 8 - 8 (1 bit)

UART0 : UART 0 Disable.
bits : 9 - 9 (1 bit)

UART1 : UART 1 Disable.
bits : 10 - 10 (1 bit)

I2C0 : I2C 0 Disable.
bits : 13 - 13 (1 bit)

CTB : Crypto Disable.
bits : 14 - 14 (1 bit)

TMR0 : Timer 0 Disable.
bits : 15 - 15 (1 bit)

TMR1 : Timer 1 Disable.
bits : 16 - 16 (1 bit)

TMR2 : Timer 2 Disable.
bits : 17 - 17 (1 bit)

TMR3 : Timer 3 Disable.
bits : 18 - 18 (1 bit)

ADC : ADC Clock Disable.
bits : 23 - 23 (1 bit)

I2C1 : I2C 1 Disable.
bits : 28 - 28 (1 bit)

FWS : Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
bits : 0 - 2 (3 bit)

RAMWS_EN : System RAM Wait State enable
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

RAM0LS_EN : System RAM 0 Light Sleep Mode.
bits : 8 - 8 (1 bit)

Enumeration:

End of enumeration elements list.

RAM1LS_EN : System RAM 1 Light Sleep Mode.
bits : 9 - 9 (1 bit)

RAM2LS_EN : System RAM 2 Light Sleep Mode.
bits : 10 - 10 (1 bit)

RAM3LS_EN : System RAM 3 Light Sleep Mode.
bits : 11 - 11 (1 bit)

ICC0LS_EN : ICache RAM Light Sleep Mode.
bits : 12 - 12 (1 bit)

ROMLS_EN : ROM Light Sleep Mode.
bits : 13 - 13 (1 bit)

RAM0 : System RAM 0 Block.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

RAM1 : System RAM 1 zeroization.
bits : 1 - 1 (1 bit)

RAM2 : System RAM 2 zeroization.
bits : 2 - 2 (1 bit)

RAMCB : System RAM check bit zeroization.
bits : 3 - 3 (1 bit)

ICC0 : Instruction Cache.
bits : 4 - 4 (1 bit)

DMA : DMA Reset.
bits : 0 - 0 (1 bit)

Enumeration: reset ( read-write )

End of enumeration elements list.

WDT0 : Watchdog Timer Reset.
bits : 1 - 1 (1 bit)

GPIO0 : GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.
bits : 2 - 2 (1 bit)

GPIO1 : GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.
bits : 3 - 3 (1 bit)

TMR0 : Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.
bits : 5 - 5 (1 bit)

TMR1 : Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.
bits : 6 - 6 (1 bit)

TMR2 : Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.
bits : 7 - 7 (1 bit)

TMR3 : Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.
bits : 8 - 8 (1 bit)

UART0 : UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.
bits : 11 - 11 (1 bit)

UART1 : UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.
bits : 12 - 12 (1 bit)

SPI0 : SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.
bits : 13 - 13 (1 bit)

SPI1 : SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.
bits : 14 - 14 (1 bit)

SPI2 : SPI2 Reset. Setting this bit to 1 resets all SPI 1 blocks.
bits : 15 - 15 (1 bit)

I2C0 : I2C0 Reset.
bits : 16 - 16 (1 bit)

RTC : Real Time Clock Reset.
bits : 17 - 17 (1 bit)

CTB : Crypto Toolbox Reset.
bits : 18 - 18 (1 bit)

TRNG : TRNG Reset.
bits : 24 - 24 (1 bit)

ADC : ADC Reset.
bits : 26 - 26 (1 bit)

UART2 : UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.
bits : 28 - 28 (1 bit)

SOFT : Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.
bits : 29 - 29 (1 bit)

PERIPH : Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.
bits : 30 - 30 (1 bit)

SYS : System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.
bits : 31 - 31 (1 bit)

ICELOCK : ARM ICE Lock Status.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

I2C1 : I2C1 Reset.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

WDT1 : WDT1 Reset.
bits : 8 - 8 (1 bit)

AES : WDT1 Reset.
bits : 10 - 10 (1 bit)

AC : AC Reset.
bits : 14 - 14 (1 bit)

I2C2 : I2C2 Reset.
bits : 17 - 17 (1 bit)

I2S : I2S Reset.
bits : 23 - 23 (1 bit)

QDEC : QDEC Reset.
bits : 25 - 25 (1 bit)

UART2 : UART2 Disable.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

TRNG : TRNG Disable.
bits : 2 - 2 (1 bit)

WDT0 : WDT0 Disable.
bits : 4 - 4 (1 bit)

WDT1 : WDT1 Disable.
bits : 5 - 5 (1 bit)

ICC0 : ICACHE Disable.
bits : 11 - 11 (1 bit)

AES : AES Clock Disable.
bits : 15 - 15 (1 bit)

I2C2 : I2C2 Disable.
bits : 21 - 21 (1 bit)

I2S : I2S Clock Disable.
bits : 23 - 23 (1 bit)

QDEC : Quadrature Decoder Interface Clock Disable.
bits : 25 - 25 (1 bit)

DMA : Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

RX : Enable RXEV pin event. When this bit is set, a logic high of GPIO0[20] (AF1) will cause an RXEV event to wake the CPU from WFE sleep mode.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

TX : Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[21] (AF1).
bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

REVISION : Manufacturer Chip Revision.
bits : 0 - 15 (16 bit)

ICEUNLOCK : ARM ICE Unlock Interrupt Enable.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

RAM0 : ECC System RAM0 Error Flag. Write 1 to clear.
bits : 0 - 0 (1 bit)

RAM1 : ECC System RAM1 Error Flag. Write 1 to clear.
bits : 1 - 1 (1 bit)

RAM2 : ECC System RAM2 Error Flag. Write 1 to clear.
bits : 2 - 2 (1 bit)

ICC0 : ECC Icache Error Flag. Write 1 to clear.
bits : 3 - 3 (1 bit)

FLASH0 : ECC Flash0 Error Flag. Write 1 to clear.
bits : 4 - 4 (1 bit)

FLASH1 : ECC Flash1 Error Flag. Write 1 to clear.
bits : 5 - 5 (1 bit)

RAM0 : ECC System RAM0 Error Flag. Write 1 to clear.
bits : 0 - 0 (1 bit)

RAM1 : ECC System RAM1 Error Flag. Write 1 to clear.
bits : 1 - 1 (1 bit)

RAM2 : ECC System RAM2 Error Flag. Write 1 to clear.
bits : 2 - 2 (1 bit)

ICC0 : ECC Icache Error Flag. Write 1 to clear.
bits : 3 - 3 (1 bit)

FLASH0 : ECC Flash0 Error Flag. Write 1 to clear.
bits : 4 - 4 (1 bit)

FLASH1 : ECC Flash1 Error Flag. Write 1 to clear.
bits : 5 - 5 (1 bit)

RAM0 : ECC System RAM0 Error interrupt enable.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

RAM1 : ECC System RAM1 Error interrupt enable.
bits : 1 - 1 (1 bit)

RAM2 : ECC System RAM2 Error interrupt enable.
bits : 2 - 2 (1 bit)

ICC0 : ECC Icache Error interrupt enable.
bits : 3 - 3 (1 bit)

FLASH0 : ECC Flash0 Error interrupt enable.
bits : 4 - 4 (1 bit)

FLASH1 : ECC Flash1 Error interrupt enable.
bits : 5 - 5 (1 bit)

DATARAMADDR : ECC Error Address/TAG RAM Error Address.
bits : 0 - 13 (14 bit)

DATARAMBANK : ECC Error Address/DATA RAM Error Bank.
bits : 14 - 14 (1 bit)

DATARAMERR : ECC Error Address/DATA RAM Error Address.
bits : 15 - 15 (1 bit)

TAGRAMADDR : ECC Error Address/TAG RAM Error Address.
bits : 16 - 29 (14 bit)

TAGRAMBANK : ECC Error Address/TAG RAM Error Bank.
bits : 30 - 30 (1 bit)

TAGRAMERR : ECC Error Address/TAG RAM Error.
bits : 31 - 31 (1 bit)

SYSCLK_DIV : Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.
bits : 6 - 8 (3 bit)

Enumeration:

End of enumeration elements list.

SYSCLK_SEL : Clock Source Select. This 3 bit field selects the source for the system clock.
bits : 9 - 11 (3 bit)

Enumeration:

End of enumeration elements list.

SYSCLK_RDY : Clock Ready. This read only bit reflects whether the currently selected system clock source is running.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

IPO_DIV : Divides the HIRC96M clock before the system clock prescaler, will affect HIRC96M Autocalibration.
bits : 14 - 15 (2 bit)

Enumeration:

End of enumeration elements list.

ERFO_EN : 32MHz Crystal Oscillator Enable.
bits : 16 - 16 (1 bit)

Enumeration:

End of enumeration elements list.

IPO_EN : 96MHz High Frequency Internal Reference Clock Enable.
bits : 19 - 19 (1 bit)

IBRO_EN : 8MHz High Frequency Internal Reference Clock Enable.
bits : 20 - 20 (1 bit)

IBRO_VS : 8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M.
bits : 21 - 21 (1 bit)

Enumeration:

End of enumeration elements list.

ERFO_RDY : 32MHz Crystal Oscillator Ready
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ERTCO_RDY : 32kHz Crystal Oscillator Ready
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

IPO_RDY : 96MHz HIRC Ready.
bits : 27 - 27 (1 bit)

IBRO_RDY : 8MHz HIRC Ready.
bits : 28 - 28 (1 bit)

INRO_RDY : 8kHz Low Frequency Reference Clock Ready.
bits : 29 - 29 (1 bit)

EXTCLK_RDY : External Clock (GPIO0[11] AF2)
bits : 31 - 31 (1 bit)

MODE : Operating Mode. This three bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.
bits : 0 - 2 (3 bit)

Enumeration:

End of enumeration elements list.

GPIO_WE : GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

RTC_WE : RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.
bits : 5 - 5 (1 bit)

LPTMR0_WE : TIMER4 Wake Up Enable. This bit enables TIMER4 as wakeup source.
bits : 6 - 6 (1 bit)

LPTMR1_WE : TIMER5 Wake Up Enable. This bit enables TIMER5 as wakeup source.
bits : 7 - 7 (1 bit)

LPUART0_WE : LPUART3 Wake Up Enable. This bit enables LPUART3 as wakeup source.
bits : 8 - 8 (1 bit)

AINCOMP_WE : AINCOMP Wake Up Enable. This bit enables AINCOMP as wakeup source.
bits : 9 - 9 (1 bit)

ERFO_PD : 32MHz power down. This bit selects 32MHz Crystal power state in DEEPSLEEP mode.
bits : 12 - 12 (1 bit)

Enumeration:

End of enumeration elements list.

IPO_PD : 96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode.
bits : 16 - 16 (1 bit)

IBRO_PD : 8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode.
bits : 17 - 17 (1 bit)

ERFO_BP : 32MHz Oscillator Bypass
bits : 20 - 20 (1 bit)

Enumeration:

End of enumeration elements list.