\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
Control Register0.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EN : I2C Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : dis
Disable I2C.
1 : en
enable I2C.
End of enumeration elements list.
MST_MODE : Master Mode Enable.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : slave_mode
Slave Mode.
1 : master_mode
Master Mode.
End of enumeration elements list.
GC_ADDR_EN : General Call Address Enable.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : dis
Ignore Gneral Call Address.
1 : en
Acknowledge general call address.
End of enumeration elements list.
IRXM_EN : Interactive Receive Mode.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : dis
Disable Interactive Receive Mode.
1 : en
Enable Interactive Receive Mode.
End of enumeration elements list.
IRXM_ACK : Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : ack
return ACK (pulling SDA LOW).
1 : nack
return NACK (leaving SDA HIGH).
End of enumeration elements list.
SCL_OUT : SCL Output. This bits control SCL output when SWOE =1.
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : drive_scl_low
Drive SCL low.
1 : release_scl
Release SCL.
End of enumeration elements list.
SDA_OUT : SDA Output. This bits control SDA output when SWOE = 1.
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : drive_sda_low
Drive SDA low.
1 : release_sda
Release SDA.
End of enumeration elements list.
SCL : SCL status. This bit reflects the logic gate of SCL signal.
bits : 8 - 16 (9 bit)
access : read-only
SDA : SDA status. THis bit reflects the logic gate of SDA signal.
bits : 9 - 18 (10 bit)
access : read-only
BB_MODE : Software Output Enable.
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
0 : outputs_disable
I2C Outputs SCLO and SDAO disabled.
1 : outputs_enable
I2C Outputs SCLO and SDAO enabled.
End of enumeration elements list.
READ : Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.
bits : 11 - 22 (12 bit)
access : read-only
Enumeration:
0 : write
Write.
1 : read
Read.
End of enumeration elements list.
CLKSTR_DIS : This bit will disable slave clock stretching when set.
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
0 : en
Slave clock stretching enabled.
1 : dis
Slave clock stretching disabled.
End of enumeration elements list.
ONE_MST_MODE : SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
0 : dis
Standard open-drain operation: drive low for 0, Hi-Z for 1
1 : en
Non-standard push-pull operation: drive low for 0, drive high for 1
End of enumeration elements list.
HS_EN : High speed mode enable
bits : 15 - 30 (16 bit)
access : read-write
Interrupt Status Register 1.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_OV : Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.
bits : 0 - 0 (1 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
TX_UN : Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).
bits : 1 - 2 (2 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
START : START Condition Status Flag.
bits : 2 - 4 (3 bit)
Interrupt Staus Register 1.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_OV : Receiver Overflow Interrupt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
No Interrupt is Pending.
1 : en
An interrupt is pending.
End of enumeration elements list.
TX_UN : Transmit Underflow Interrupt Enable.
bits : 1 - 2 (2 bit)
Enumeration:
0 : dis
No Interrupt is Pending.
1 : en
An interrupt is pending.
End of enumeration elements list.
START : START Condition Interrupt Enable.
bits : 2 - 4 (3 bit)
FIFO Configuration Register.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_DEPTH : Receive FIFO Length.
bits : 0 - 7 (8 bit)
access : read-only
TX_DEPTH : Transmit FIFO Length.
bits : 8 - 23 (16 bit)
access : read-only
Receive Control Register 0.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DNR : Do Not Respond.
bits : 0 - 0 (1 bit)
Enumeration:
0 : respond
Always respond to address match.
1 : not_respond_rx_fifo_empty
Do not respond to address match when RX_FIFO is not empty.
End of enumeration elements list.
FLUSH : Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.
bits : 7 - 14 (8 bit)
Enumeration:
0 : not_flushed
FIFO not flushed.
1 : flush
Flush RX_FIFO.
End of enumeration elements list.
THD_LVL : Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.
bits : 8 - 19 (12 bit)
Receive Control Register 1.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.
bits : 0 - 7 (8 bit)
LVL : Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.
bits : 8 - 19 (12 bit)
access : read-only
Transmit Control Register 0.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRELOAD_MODE : Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.
bits : 0 - 0 (1 bit)
TX_READY_MODE : Transmit FIFO Ready Manual Mode.
bits : 1 - 2 (2 bit)
Enumeration:
0 : en
HW control of I2CTXRDY enabled.
1 : dis
HW control of I2CTXRDY disabled.
End of enumeration elements list.
GC_ADDR_FLUSH_DIS : TX FIFO General Call Address Match Auto Flush Disable.
bits : 2 - 4 (3 bit)
Enumeration:
0 : en
Enabled.
1 : dis
Disabled.
End of enumeration elements list.
WR_ADDR_FLUSH_DIS : TX FIFO Slave Address Match Write Auto Flush Disable.
bits : 3 - 6 (4 bit)
Enumeration:
0 : en
Enabled.
1 : dis
Disabled.
End of enumeration elements list.
RD_ADDR_FLUSH_DIS : TX FIFO Slave Address Match Read Auto Flush Disable.
bits : 4 - 8 (5 bit)
Enumeration:
0 : en
Enabled.
1 : dis
Disabled.
End of enumeration elements list.
NACK_FLUSH_DIS : TX FIFO received NACK Auto Flush Disable.
bits : 5 - 10 (6 bit)
Enumeration:
0 : en
Enabled.
1 : dis
Disabled.
End of enumeration elements list.
FLUSH : Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.
bits : 7 - 14 (8 bit)
Enumeration:
0 : not_flushed
FIFO not flushed.
1 : flush
Flush TX_FIFO.
End of enumeration elements list.
THD_VAL : Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.
bits : 8 - 19 (12 bit)
Transmit Control Register 1.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRELOAD_RDY : Transmit FIFO Preload Ready.
bits : 0 - 0 (1 bit)
LVL : Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.
bits : 8 - 19 (12 bit)
access : read-only
Data Register.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.
bits : 0 - 7 (8 bit)
Master Control Register.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
START : Setting this bit to 1 will start a master transfer.
bits : 0 - 0 (1 bit)
RESTART : Setting this bit to 1 will generate a repeated START.
bits : 1 - 2 (2 bit)
STOP : Setting this bit to 1 will generate a STOP condition.
bits : 2 - 4 (3 bit)
EX_ADDR_EN : Slave Extend Address Select.
bits : 7 - 14 (8 bit)
Enumeration:
0 : 7_bits_address
7-bit address.
1 : 10_bits_address
10-bit address.
End of enumeration elements list.
Clock Low Register.
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LO : Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.
bits : 0 - 8 (9 bit)
Clock high Register.
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HI : Clock High. In master mode, these bits define the SCL high period.
bits : 0 - 8 (9 bit)
Clock high Register.
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LO : Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA.
bits : 0 - 7 (8 bit)
HI : Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA
bits : 8 - 23 (16 bit)
Status Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : Bus Status.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : idle
I2C Bus Idle.
1 : busy
I2C Bus Busy.
End of enumeration elements list.
RX_EM : RX empty.
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0 : not_empty
Not Empty.
1 : empty
Empty.
End of enumeration elements list.
RX_FULL : RX Full.
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
0 : not_full
Not Full.
1 : full
Full.
End of enumeration elements list.
TX_EM : TX Empty.
bits : 3 - 6 (4 bit)
Enumeration:
0 : not_empty
Not Empty.
1 : empty
Empty.
End of enumeration elements list.
TX_FULL : TX Full.
bits : 4 - 8 (5 bit)
Enumeration:
0 : not_empty
Not Empty.
1 : empty
Empty.
End of enumeration elements list.
MST_BUSY : Clock Mode.
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : not_actively_driving_scl_clock
Device not actively driving SCL clock cycles.
1 : actively_driving_scl_clock
Device operating as master and actively driving SCL clock cycles.
End of enumeration elements list.
Timeout Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SCL_TO_VAL : Timeout
bits : 0 - 15 (16 bit)
Slave Address Register.
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Slave Address.
bits : 0 - 9 (10 bit)
EXT_ADDR_EN : Extended Address Select.
bits : 15 - 30 (16 bit)
Enumeration:
0 : 7_bits_address
7-bit address.
1 : 10_bits_address
10-bit address.
End of enumeration elements list.
DMA Register.
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_EN : TX channel enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RX_EN : RX channel enable.
bits : 1 - 2 (2 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
Interrupt Status Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DONE : Transfer Done Interrupt.
bits : 0 - 0 (1 bit)
Enumeration: INT_FL0_Done
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
IRXM : Interactive Receive Interrupt.
bits : 1 - 2 (2 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
GC_ADDR_MATCH : Slave General Call Address Match Interrupt.
bits : 2 - 4 (3 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
ADDR_MATCH : Slave Address Match Interrupt.
bits : 3 - 6 (4 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
RX_THD : Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.
bits : 4 - 8 (5 bit)
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending. RX_FIFO equal or more bytes than the threshold.
End of enumeration elements list.
TX_THD : Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.
bits : 5 - 10 (6 bit)
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
End of enumeration elements list.
STOP : STOP Interrupt.
bits : 6 - 12 (7 bit)
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
End of enumeration elements list.
ADDR_ACK : Address Acknowledge Interrupt.
bits : 7 - 14 (8 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
ARB_ERR : Arbritation error Interrupt.
bits : 8 - 16 (9 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
TO_ERR : timeout Error Interrupt.
bits : 9 - 18 (10 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
ADDR_NACK_ERR : Address NACK Error Interrupt.
bits : 10 - 20 (11 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
DATA_ERR : Data NACK Error Interrupt.
bits : 11 - 22 (12 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
DNR_ERR : Do Not Respond Error Interrupt.
bits : 12 - 24 (13 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
START_ERR : Start Error Interrupt.
bits : 13 - 26 (14 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
STOP_ERR : Stop Error Interrupt.
bits : 14 - 28 (15 bit)
Enumeration:
0 : inactive
No Interrupt is Pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
TX_LOCKOUT : Transmit Lock Out Interrupt.
bits : 15 - 30 (16 bit)
MAMI : Multiple Address Match Interrupt
bits : 16 - 37 (22 bit)
RD_ADDR_MATCH : Slave Read Address Match Interrupt
bits : 22 - 44 (23 bit)
WR_ADDR_MATCH : Slave Write Address Match Interrupt
bits : 23 - 46 (24 bit)
Interrupt Enable Register.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : Transfer Done Interrupt Enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled when DONE = 1.
End of enumeration elements list.
IRXM : Description not available.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled when RX_MODE = 1.
End of enumeration elements list.
GC_ADDR_MATCH : Slave mode general call address match received input enable.
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled when GEN_CTRL_ADDR = 1.
End of enumeration elements list.
ADDR_MATCH : Slave mode incoming address match interrupt.
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled when ADDR_MATCH = 1.
End of enumeration elements list.
RX_THD : RX FIFO Above Treshold Level Interrupt Enable.
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
TX_THD : TX FIFO Below Treshold Level Interrupt Enable.
bits : 5 - 10 (6 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
STOP : Stop Interrupt Enable
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled when STOP = 1.
End of enumeration elements list.
ADDR_ACK : Received Address ACK from Slave Interrupt.
bits : 7 - 14 (8 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
ARB_ERR : Master Mode Arbitration Lost Interrupt.
bits : 8 - 16 (9 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
TO_ERR : Timeout Error Interrupt Enable.
bits : 9 - 18 (10 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
ADDR_NACK_ERR : Master Mode Address NACK Received Interrupt.
bits : 10 - 20 (11 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
DATA_ERR : Master Mode Data NACK Received Interrupt.
bits : 11 - 22 (12 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
DNR_ERR : Slave Mode Do Not Respond Interrupt.
bits : 12 - 24 (13 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
START_ERR : Out of Sequence START condition detected interrupt.
bits : 13 - 26 (14 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
STOP_ERR : Out of Sequence STOP condition detected interrupt.
bits : 14 - 28 (15 bit)
Enumeration:
0 : dis
Interrupt disabled.
1 : en
Interrupt enabled.
End of enumeration elements list.
TX_LOCKOUT : TX FIFO Locked Out Interrupt.
bits : 15 - 30 (16 bit)
MAMI : Multiple Address Match Interrupt
bits : 16 - 37 (22 bit)
RD_ADDR_MATCH : Slave Read Address Match Interrupt
bits : 22 - 44 (23 bit)
WR_ADDR_MATCH : Slave Write Address Match Interrupt
bits : 23 - 46 (24 bit)
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