CTRL0CH0

CTRL1CH0

FILTCH0

DMACH0

FIFOCH0

INTFL

INTEN

EXTSETUP

WKEN

WKFL

LSB_FIRST : LSB Transmit Receive First.
bits : 1 - 2 (2 bit)
access : read-write

PDM_FILT : PDM Filter.
bits : 2 - 4 (3 bit)
access : read-write

PDM_EN : PDM Enable.
bits : 3 - 6 (4 bit)
access : read-write

USEDDR : DDR.
bits : 4 - 8 (5 bit)
access : read-write

PDM_INV : Invert PDM.
bits : 5 - 10 (6 bit)
access : read-write

CH_MODE : SCK Select.
bits : 6 - 13 (8 bit)
access : read-write

WS_POL : WS polarity select.
bits : 8 - 16 (9 bit)
access : read-write

MSB_LOC : MSB location.
bits : 9 - 18 (10 bit)
access : read-only

ALIGN : Align to MSB or LSB.
bits : 10 - 20 (11 bit)
access : read-only

EXT_SEL : External SCK/WS selection.
bits : 11 - 22 (12 bit)
access : read-write

STEREO : Stereo mode of I2S.
bits : 12 - 25 (14 bit)
access : read-only

WSIZE : Data size when write to FIFO.
bits : 14 - 29 (16 bit)
access : read-write

TX_EN : TX channel enable.
bits : 16 - 32 (17 bit)
access : read-write

RX_EN : RX channel enable.
bits : 17 - 34 (18 bit)
access : read-write

FLUSH : Flushes the TX/RX FIFO buffer.
bits : 18 - 36 (19 bit)
access : read-write

RST : Write 1 to reset channel.
bits : 19 - 38 (20 bit)
access : read-write

FIFO_LSB : Bit Field Control.
bits : 20 - 40 (21 bit)
access : read-write

RX_THD_VAL : depth of receive FIFO for threshold interrupt generation.
bits : 24 - 55 (32 bit)
access : read-write

BITS_WORD : I2S word length.
bits : 0 - 4 (5 bit)
access : read-write

EN : I2S clock enable.
bits : 8 - 16 (9 bit)
access : read-write

SMP_SIZE : I2S sample size length.
bits : 9 - 22 (14 bit)
access : read-write

ADJUST : LSB/MSB Justify.
bits : 15 - 30 (16 bit)
access : read-write

CLKDIV : I2S clock frequency divisor.
bits : 16 - 47 (32 bit)
access : read-write

DMA_TX_THD_VAL : TX FIFO Level DMA Trigger.
bits : 0 - 6 (7 bit)
access : read-write

DMA_TX_EN : TX DMA channel enable.
bits : 7 - 14 (8 bit)
access : read-write

DMA_RX_THD_VAL : RX FIFO Level DMA Trigger.
bits : 8 - 22 (15 bit)
access : read-write

DMA_RX_EN : RX DMA channel enable.
bits : 15 - 30 (16 bit)
access : read-write

TX_LVL : Number of data word in the TX FIFO.
bits : 16 - 39 (24 bit)
access : read-write

RX_LVL : Number of data word in the RX FIFO.
bits : 24 - 55 (32 bit)
access : read-write

DATA : Load/unload location for TX and RX FIFO buffers.
bits : 0 - 31 (32 bit)
access : read-write

RX_OV_CH0 : Status for RX FIFO Overrun interrupt.
bits : 0 - 0 (1 bit)
access : read-write

RX_THD_CH0 : Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
bits : 1 - 2 (2 bit)
access : read-write

TX_OB_CH0 : Status for interrupt when TX FIFO has only one byte remaining.
bits : 2 - 4 (3 bit)
access : read-write

TX_HE_CH0 : Status for interrupt when TX FIFO is half empty.
bits : 3 - 6 (4 bit)
access : read-write

RX_OV_CH0 : Enable for RX FIFO Overrun interrupt.
bits : 0 - 0 (1 bit)
access : read-write

RX_THD_CH0 : Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
bits : 1 - 2 (2 bit)
access : read-write

TX_OB_CH0 : Enable for interrupt when TX FIFO has only one byte remaining.
bits : 2 - 4 (3 bit)
access : read-write

TX_HE_CH0 : Enable for interrupt when TX FIFO is half empty.
bits : 3 - 6 (4 bit)
access : read-write

EXT_BITS_WORD : Word Length for ch_mode.
bits : 0 - 4 (5 bit)
access : read-write