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ICC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

INFO

CTRL

SZ

INVALIDATE


INFO

Cache ID Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INFO INFO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELNUM PARTNUM ID

RELNUM : Release Number. Identifies the RTL release version.
bits : 0 - 5 (6 bit)

PARTNUM : Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.
bits : 6 - 9 (4 bit)

ID : Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.
bits : 10 - 15 (6 bit)


CTRL

Cache Control and Status Register.
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN RDY

EN : Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.

1 : en

Cache Enabled.

End of enumeration elements list.

RDY : Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

0 : notReady

Not Ready.

1 : ready

Ready.

End of enumeration elements list.


SZ

Memory Configuration Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SZ SZ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCH MEM

CCH : Cache Size. Indicates total size in Kbytes of cache.
bits : 0 - 15 (16 bit)

MEM : Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.
bits : 16 - 31 (16 bit)


INVALIDATE

Invalidate All Registers.
address_offset : 0x700 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INVALIDATE INVALIDATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVALID

INVALID : Invalidate.
bits : 0 - 31 (32 bit)



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