\n

PWRSEQ

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

LPCN

LPWKEN1

LPPWKST

LPPWKEN

LPWKST0

LPMEMSD

GPR0

GPR1

LPWKEN0

LPWKST1


LPCN

Low Power Control Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPCN LPCN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM0RET_EN RAM1RET_EN RAM2RET_EN RAM3RET_EN OVR VCORE_DET_BYPASS FVDDEN RETREG_EN STORAGE_EN FASTWK_EN BG_DIS VCOREPOR_DIS LDO_DIS VCORE_EXT VCOREMON_DIS VDDAMON_DIS PORVDDMON_DIS VBBMON_DIS INRO_EN ERTCO_EN TM_LPMODE TM_PWRSEQ

RAM0RET_EN : System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : dis

Disable Ram Retention.

1 : en

Enable System RAM 0 retention.

End of enumeration elements list.

RAM1RET_EN : System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : dis

Disable Ram Retention.

1 : en

Enable System RAM 1 retention.

End of enumeration elements list.

RAM2RET_EN : System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : dis

Disable Ram Retention.

1 : en

Enable System RAM 2 retention.

End of enumeration elements list.

RAM3RET_EN : System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : dis

Disable Ram Retention.

1 : en

Enable System RAM 3 retention.

End of enumeration elements list.

OVR : Operating Voltage Range
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : 0_9V

0.9V 12MHz

1 : 1_0V

1.0V 48MHz

2 : 1_1V

1.1V 96MHz

End of enumeration elements list.

VCORE_DET_BYPASS : Block Auto-Detect
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : en

enable

1 : dis

disable

End of enumeration elements list.

FVDDEN : Flash VDD Enable, force the flash VDD to remain enabled during LP modes.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : dis

enable

1 : en

disable

End of enumeration elements list.

RETREG_EN : Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : dis

Disabled.

1 : en

Enabled.

End of enumeration elements list.

STORAGE_EN : STORAGE Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : dis

Disabled.

1 : en

Enabled.

End of enumeration elements list.

FASTWK_EN : Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical).
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : dis

Disabled.

1 : en

Enabled.

End of enumeration elements list.

BG_DIS : Bandgap OFF. This controls the System Bandgap in DeepSleep mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : on

Bandgap is always ON.

1 : off

Bandgap is OFF in DeepSleep mode (default).

End of enumeration elements list.

VCOREPOR_DIS : VDDC (Vcore) Power on reset Monitor Disable.This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : en

Enable

1 : dis

Disabled.

End of enumeration elements list.

LDO_DIS : Disable Main LDO
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : en

Enable

1 : dis

Disabled.

End of enumeration elements list.

VCORE_EXT : Use external VCORE for 1V supply
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : dis

disable

1 : en

use Vcore for retention.

End of enumeration elements list.

VCOREMON_DIS : VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : en

Enable

1 : dis

Disabled.

End of enumeration elements list.

VDDAMON_DIS : VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : en

Enable if Bandgap is ON (default)

1 : dis

Disabled.

End of enumeration elements list.

PORVDDMON_DIS : VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : dis

Disabled.

1 : en

Enabled.

End of enumeration elements list.

VBBMON_DIS : VBB Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : en

Enable if Bandgap is ON (default)

1 : dis

Disabled.

End of enumeration elements list.

INRO_EN : INRO remains on in all power modes if this bit is set otherwise it is controled by the LP controller
bits : 28 - 28 (1 bit)
access : read-write

ERTCO_EN : XRTCO remains on in all power modes if this bit is set otherwise it is controled by the LP controller
bits : 29 - 29 (1 bit)
access : read-write

TM_LPMODE : TBD
bits : 30 - 30 (1 bit)
access : read-write

TM_PWRSEQ : TBD
bits : 31 - 31 (1 bit)
access : read-write


LPWKEN1

Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPWKEN1 LPWKEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LPPWKST

Low Power Peripheral Wakeup Status Register.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPPWKST LPPWKST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMR0 LPTMR1 LPUART0 AINCOMP0 AINCOMP1 AINCOMP0_OUT AINCOMP1_OUT BACKUP

LPTMR0 : LPTM0 Wakeup Flag.
bits : 0 - 0 (1 bit)
access : read-write

LPTMR1 : LPTMR1 Wakeup Flag.
bits : 1 - 1 (1 bit)
access : read-write

LPUART0 : LPUART0 Wakeup Flag.
bits : 2 - 2 (1 bit)
access : read-write

AINCOMP0 : AINCOMP0 Wakeup Flag.
bits : 3 - 3 (1 bit)
access : read-write

AINCOMP1 : AINCOMP1 Wakeup Flag.
bits : 4 - 4 (1 bit)
access : read-write

AINCOMP0_OUT : AINCOMP0 Status.
bits : 5 - 5 (1 bit)
access : read-only

AINCOMP1_OUT : AINCOMP1 Status.
bits : 6 - 6 (1 bit)
access : read-only

BACKUP : BBMODE Wakeup Flag.
bits : 16 - 16 (1 bit)
access : read-write


LPPWKEN

Low Power Peripheral Wakeup Enable Register.
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPPWKEN LPPWKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMR0 LPTMR1 LPUART0 AINCOMP0 AINCOMP1

LPTMR0 : TIMER4 Wakeup Enable. This bit allows wakeup from the TIMER4.
bits : 0 - 0 (1 bit)
access : read-write

LPTMR1 : TIMER5 Wakeup Enable. This bit allows wakeup from the TIMER5.
bits : 1 - 1 (1 bit)
access : read-write

LPUART0 : LPUART Wakeup Enable. This bit allows wakeup from the LPUART.
bits : 2 - 2 (1 bit)
access : read-write

AINCOMP0 : AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0.
bits : 3 - 3 (1 bit)
access : read-write

AINCOMP1 : AINCOMP1 Wakeup Enable. This bit allows wakeup from the AINCOMP1.
bits : 4 - 4 (1 bit)
access : read-write


LPWKST0

Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPWKST0 LPWKST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST

ST : Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.
bits : 0 - 30 (31 bit)
access : read-write


LPMEMSD

Low Power Memory Shutdown Control.
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPMEMSD LPMEMSD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM0 RAM1 RAM2 RAM3

RAM0 : System RAM block 0 Shut Down.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : normal

Normal Operating Mode.

1 : shutdown

Shutdown Mode.

End of enumeration elements list.

RAM1 : System RAM block 1 Shut Down.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : normal

Normal Operating Mode.

1 : shutdown

Shutdown Mode.

End of enumeration elements list.

RAM2 : System RAM block 2 Shut Down.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : normal

Normal Operating Mode.

1 : shutdown

Shutdown Mode.

End of enumeration elements list.

RAM3 : System RAM block 3 Shut Down.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : normal

Normal Operating Mode.

1 : shutdown

Shutdown Mode.

End of enumeration elements list.


GPR0

General Purpose Register 0.
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR0 GPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPR1

General Purpose Register 1.
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR1 GPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LPWKEN0

Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPWKEN0 LPWKEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.
bits : 0 - 30 (31 bit)
access : read-write


LPWKST1

Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPWKST1 LPWKST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.