SEC

CTRL

TRIM

OSCCTRL

SSEC

TODA

SSECA

SEC : Seconds Counter.
bits : 0 - 7 (8 bit)

EN : Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

TOD_ALARM_IE : Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

SSEC_ALARM_IE : Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

BUSY : RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDY : RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

RDY_IE : RTC Ready Interrupt Enable.
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

TOD_ALARM : Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SSEC_ALARM : Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SQW_EN : Square Wave Output Enable.
bits : 8 - 8 (1 bit)

Enumeration:

End of enumeration elements list.

SQW_SEL : Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.
bits : 9 - 10 (2 bit)

Enumeration:

End of enumeration elements list.

RD_EN : Asynchronous Counter Read Enable.
bits : 14 - 14 (1 bit)

WR_EN : Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

TRIM : RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.
bits : 0 - 7 (8 bit)

VRTC_TMR : VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.
bits : 8 - 31 (24 bit)

BYPASS : RTC Crystal Bypass
bits : 4 - 4 (1 bit)

SQW_32K : RTC 32kHz Square Wave Output
bits : 5 - 5 (1 bit)

SSEC : Sub-Seconds Counter (12-bit).
bits : 0 - 7 (8 bit)

TOD_ALARM : Time-of-day Alarm.
bits : 0 - 19 (20 bit)

SSEC_ALARM : This register contains the reload value for the sub-second alarm.
bits : 0 - 31 (32 bit)