CNT

CTRL0

NOLCMP

CTRL1

WKFL

CMP

PWM

INTFL

COUNT : The current count value for the timer. This field increments as the timer counts.
bits : 0 - 31 (32 bit)

MODE_A : Mode Select for Timer A
bits : 0 - 3 (4 bit)

Enumeration:

End of enumeration elements list.

CLKDIV_A : Clock Divider Select for Timer A
bits : 4 - 7 (4 bit)

Enumeration:

End of enumeration elements list.

POL_A : Timer Polarity for Timer A
bits : 8 - 8 (1 bit)

PWMSYNC_A : PWM Synchronization Mode for Timer A
bits : 9 - 9 (1 bit)

NOLHPOL_A : PWM Phase A (Non-Overlapping High) Polarity for Timer A
bits : 10 - 10 (1 bit)

NOLLPOL_A : PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A
bits : 11 - 11 (1 bit)

PWMCKBD_A : PWM Phase A-Prime Output Disable for Timer A
bits : 12 - 12 (1 bit)

RST_A : Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.
bits : 13 - 13 (1 bit)

CLKEN_A : Write 1 to Enable CLK_TMR for Timer A
bits : 14 - 14 (1 bit)

EN_A : Enable for Timer A
bits : 15 - 15 (1 bit)

MODE_B : Mode Select for Timer B
bits : 16 - 19 (4 bit)

Enumeration:

End of enumeration elements list.

CLKDIV_B : Clock Divider Select for Timer B
bits : 20 - 23 (4 bit)

Enumeration:

End of enumeration elements list.

POL_B : Timer Polarity for Timer B
bits : 24 - 24 (1 bit)

PWMSYNC_B : PWM Synchronization Mode for Timer B
bits : 25 - 25 (1 bit)

NOLHPOL_B : PWM Phase A (Non-Overlapping High) Polarity for Timer B
bits : 26 - 26 (1 bit)

NOLLPOL_B : PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B
bits : 27 - 27 (1 bit)

PWMCKBD_B : PWM Phase A-Prime Output Disable for Timer B
bits : 28 - 28 (1 bit)

RST_B : Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.
bits : 29 - 29 (1 bit)

CLKEN_B : Write 1 to Enable CLK_TMR for Timer B
bits : 30 - 30 (1 bit)

EN_B : Enable for Timer B
bits : 31 - 31 (1 bit)

LO_A : Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
bits : 0 - 7 (8 bit)

HI_A : Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
bits : 8 - 15 (8 bit)

LO_B : Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.
bits : 16 - 23 (8 bit)

HI_B : Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.
bits : 24 - 31 (8 bit)

CLKSEL_A : Timer Clock Select for Timer A
bits : 0 - 1 (2 bit)

CLKEN_A : Timer A Enable Status
bits : 2 - 2 (1 bit)

CLKRDY_A : CLK_TMR Ready Flag for Timer A
bits : 3 - 3 (1 bit)

EVENT_SEL_A : Event Select for Timer A
bits : 4 - 6 (3 bit)

NEGTRIG_A : Negative Edge Trigger for Event for Timer A
bits : 7 - 7 (1 bit)

IE_A : Interrupt Enable for Timer A
bits : 8 - 8 (1 bit)

CAPEVENT_SEL_A : Capture Event Select for Timer A
bits : 9 - 10 (2 bit)

SW_CAPEVENT_A : Software Capture Event for Timer A
bits : 11 - 11 (1 bit)

WE_A : Wake-Up Enable for Timer A
bits : 12 - 12 (1 bit)

OUTEN_A : OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A
bits : 13 - 13 (1 bit)

OUTBEN_A : PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A
bits : 14 - 14 (1 bit)

CLKSEL_B : Timer Clock Select for Timer B
bits : 16 - 17 (2 bit)

CLKEN_B : Timer B Enable Status
bits : 18 - 18 (1 bit)

CLKRDY_B : CLK_TMR Ready Flag for Timer B
bits : 19 - 19 (1 bit)

EVENT_SEL_B : Event Select for Timer B
bits : 20 - 22 (3 bit)

NEGTRIG_B : Negative Edge Trigger for Event for Timer B
bits : 23 - 23 (1 bit)

IE_B : Interrupt Enable for Timer B
bits : 24 - 24 (1 bit)

CAPEVENT_SEL_B : Capture Event Select for Timer B
bits : 25 - 26 (2 bit)

SW_CAPEVENT_B : Software Capture Event for Timer B
bits : 27 - 27 (1 bit)

WE_B : Wake-Up Enable for Timer B
bits : 28 - 28 (1 bit)

CASCADE : Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.
bits : 31 - 31 (1 bit)

A : Wake-Up Flag for Timer A
bits : 0 - 0 (1 bit)

B : Wake-Up Flag for Timer B
bits : 16 - 16 (1 bit)

COMPARE : The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
bits : 0 - 31 (32 bit)

PWM : Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.
bits : 0 - 31 (32 bit)

IRQ_A : Interrupt Flag for Timer A.
bits : 0 - 0 (1 bit)

WRDONE_A : Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.
bits : 8 - 8 (1 bit)

WR_DIS_A : Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.
bits : 9 - 9 (1 bit)

IRQ_B : Interrupt Flag for Timer B.
bits : 16 - 16 (1 bit)

WRDONE_B : Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.
bits : 24 - 24 (1 bit)

WR_DIS_B : Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.
bits : 25 - 25 (1 bit)