CTRL

CLKDIV

OSR

TXPEEK

PNR

FIFO

DMA

WKEN

WKFL

STATUS

INT_EN

INT_FL

RX_THD_VAL : This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)
bits : 0 - 3 (4 bit)

PAR_EN : Parity Enable
bits : 4 - 4 (1 bit)

PAR_EO : when PAREN=1 selects odd or even parity odd is 1 even is 0
bits : 5 - 5 (1 bit)

PAR_MD : Selects parity based on 1s or 0s count (when PAREN=1)
bits : 6 - 6 (1 bit)

CTS_DIS : CTS Sampling Disable
bits : 7 - 7 (1 bit)

TX_FLUSH : Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.
bits : 8 - 8 (1 bit)

RX_FLUSH : Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.
bits : 9 - 9 (1 bit)

CHAR_SIZE : Selects UART character size
bits : 10 - 11 (2 bit)

Enumeration:

End of enumeration elements list.

STOPBITS : Selects the number of stop bits that will be generated
bits : 12 - 12 (1 bit)

HFC_EN : Enables/disables hardware flow control
bits : 13 - 13 (1 bit)

RTSDC : Hardware Flow Control RTS Mode
bits : 14 - 14 (1 bit)

BCLKEN : Baud clock enable
bits : 15 - 15 (1 bit)

BCLKSRC : To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock.
bits : 16 - 17 (2 bit)

Enumeration:

End of enumeration elements list.

DPFE_EN : Data/Parity bit frame error detection enable
bits : 18 - 18 (1 bit)

BCLKRDY : Baud clock Ready read only bit
bits : 19 - 19 (1 bit)

UCAGM : UART Clock Auto Gating mode
bits : 20 - 20 (1 bit)

FDM : Fractional Division Mode
bits : 21 - 21 (1 bit)

DESM : RX Dual Edge Sampling Mode
bits : 22 - 22 (1 bit)

CLKDIV : Baud rate divisor value
bits : 0 - 19 (20 bit)

OSR : OSR
bits : 0 - 2 (3 bit)

DATA : Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field.
bits : 0 - 7 (8 bit)

CTS : Current sampled value of CTS IO
bits : 0 - 0 (1 bit)
access : read-only

RTS : This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level.
bits : 1 - 1 (1 bit)

DATA : Load/unload location for TX and RX FIFO buffers.
bits : 0 - 7 (8 bit)

RX_PAR : Parity error flag for next byte to be read from FIFO.
bits : 8 - 8 (1 bit)

TX_THD_VAL : TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory.
bits : 0 - 3 (4 bit)

TX_EN : TX DMA channel enable
bits : 4 - 4 (1 bit)

RX_THD_VAL : Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory.
bits : 5 - 8 (4 bit)

RX_EN : RX DMA channel enable
bits : 9 - 9 (1 bit)

RX_NE : Wake-Up Enable for RX FIFO Not Empty
bits : 0 - 0 (1 bit)

RX_FULL : Wake-Up Enable for RX FIFO Full
bits : 1 - 1 (1 bit)

RX_THD : Wake-Up Enable for RX FIFO Threshold Met
bits : 2 - 2 (1 bit)

RX_NE : Wake-Up Flag for RX FIFO Not Empty
bits : 0 - 0 (1 bit)

RX_FULL : Wake-Up Flag for RX FIFO Full
bits : 1 - 1 (1 bit)

RX_THD : Wake-Up Flag for RX FIFO Threshold Met
bits : 2 - 2 (1 bit)

TX_BUSY : Read-only flag indicating the UART transmit status
bits : 0 - 0 (1 bit)

RX_BUSY : Read-only flag indicating the UART receiver status
bits : 1 - 1 (1 bit)

RX_EM : Read-only flag indicating the RX FIFO state
bits : 4 - 4 (1 bit)

RX_FULL : Read-only flag indicating the RX FIFO state
bits : 5 - 5 (1 bit)

TX_EM : Read-only flag indicating the TX FIFO state
bits : 6 - 6 (1 bit)

TX_FULL : Read-only flag indicating the TX FIFO state
bits : 7 - 7 (1 bit)

RX_LVL : Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)
bits : 8 - 11 (4 bit)

TX_LVL : Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)
bits : 12 - 15 (4 bit)

RX_FERR : Enable Interrupt For RX Frame Error
bits : 0 - 0 (1 bit)

RX_PAR : Enable Interrupt For RX Parity Error
bits : 1 - 1 (1 bit)

CTS_EV : Enable Interrupt For CTS signal change Error
bits : 2 - 2 (1 bit)

RX_OV : Enable Interrupt For RX FIFO Overrun Error
bits : 3 - 3 (1 bit)

RX_THD : Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD
bits : 4 - 4 (1 bit)

TX_HE : Enable Interrupt For TX FIFO has half empty
bits : 6 - 6 (1 bit)

RX_FERR : Flag for RX Frame Error Interrupt.
bits : 0 - 0 (1 bit)

RX_PAR : Flag for RX Parity Error interrupt
bits : 1 - 1 (1 bit)

CTS_EV : Flag for CTS signal change interrupt (hardware flow control disabled)
bits : 2 - 2 (1 bit)

RX_OV : Flag for RX FIFO Overrun interrupt
bits : 3 - 3 (1 bit)

RX_THD : Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field
bits : 4 - 4 (1 bit)

TX_HE : Flag for interrupt when TX FIFO is half empty
bits : 6 - 6 (1 bit)