Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Watchdog Timer Control Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_LATE_VAL : Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.
bits : 0 - 3 (4 bit)
Enumeration:
0 : wdt2pow31
2**31 clock cycles.
1 : wdt2pow30
2**30 clock cycles.
2 : wdt2pow29
2**29 clock cycles.
3 : wdt2pow28
2**28 clock cycles.
4 : wdt2pow27
2^27 clock cycles.
5 : wdt2pow26
2**26 clock cycles.
6 : wdt2pow25
2**25 clock cycles.
7 : wdt2pow24
2**24 clock cycles.
8 : wdt2pow23
2**23 clock cycles.
9 : wdt2pow22
2**22 clock cycles.
10 : wdt2pow21
2**21 clock cycles.
11 : wdt2pow20
2**20 clock cycles.
12 : wdt2pow19
2**19 clock cycles.
13 : wdt2pow18
2**18 clock cycles.
14 : wdt2pow17
2**17 clock cycles.
15 : wdt2pow16
2**16 clock cycles.
End of enumeration elements list.
RST_LATE_VAL : Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
bits : 4 - 7 (4 bit)
Enumeration:
0 : wdt2pow31
2**31 clock cycles.
1 : wdt2pow30
2**30 clock cycles.
2 : wdt2pow29
2**29 clock cycles.
3 : wdt2pow28
2**28 clock cycles.
4 : wdt2pow27
2^27 clock cycles.
5 : wdt2pow26
2**26 clock cycles.
6 : wdt2pow25
2**25 clock cycles.
7 : wdt2pow24
2**24 clock cycles.
8 : wdt2pow23
2**23 clock cycles.
9 : wdt2pow22
2**22 clock cycles.
10 : wdt2pow21
2**21 clock cycles.
11 : wdt2pow20
2**20 clock cycles.
12 : wdt2pow19
2**19 clock cycles.
13 : wdt2pow18
2**18 clock cycles.
14 : wdt2pow17
2**17 clock cycles.
15 : wdt2pow16
2**16 clock cycles.
End of enumeration elements list.
EN : Windowed Watchdog Timer Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
INT_LATE : Windowed Watchdog Timer Interrupt Flag Too Late.
bits : 9 - 9 (1 bit)
Enumeration: ( read-write )
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
WDT_INT_EN : Windowed Watchdog Timer Interrupt Enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
WDT_RST_EN : Windowed Watchdog Timer Reset Enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
INT_EARLY : Windowed Watchdog Timer Interrupt Flag Too Soon.
bits : 12 - 12 (1 bit)
Enumeration: ( read-write )
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
INT_EARLY_VAL : Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.
bits : 16 - 19 (4 bit)
Enumeration:
0 : wdt2pow31
2**31 clock cycles.
1 : wdt2pow30
2**30 clock cycles.
2 : wdt2pow29
2**29 clock cycles.
3 : wdt2pow28
2**28 clock cycles.
4 : wdt2pow27
2^27 clock cycles.
5 : wdt2pow26
2**26 clock cycles.
6 : wdt2pow25
2**25 clock cycles.
7 : wdt2pow24
2**24 clock cycles.
8 : wdt2pow23
2**23 clock cycles.
9 : wdt2pow22
2**22 clock cycles.
10 : wdt2pow21
2**21 clock cycles.
11 : wdt2pow20
2**20 clock cycles.
12 : wdt2pow19
2**19 clock cycles.
13 : wdt2pow18
2**18 clock cycles.
14 : wdt2pow17
2**17 clock cycles.
15 : wdt2pow16
2**16 clock cycles.
End of enumeration elements list.
RST_EARLY_VAL : Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.
bits : 20 - 23 (4 bit)
Enumeration:
0 : wdt2pow31
2**31 clock cycles.
1 : wdt2pow30
2**30 clock cycles.
2 : wdt2pow29
2**29 clock cycles.
3 : wdt2pow28
2**28 clock cycles.
4 : wdt2pow27
2^27 clock cycles.
5 : wdt2pow26
2**26 clock cycles.
6 : wdt2pow25
2**25 clock cycles.
7 : wdt2pow24
2**24 clock cycles.
8 : wdt2pow23
2**23 clock cycles.
9 : wdt2pow22
2**22 clock cycles.
10 : wdt2pow21
2**21 clock cycles.
11 : wdt2pow20
2**20 clock cycles.
12 : wdt2pow19
2**19 clock cycles.
13 : wdt2pow18
2**18 clock cycles.
14 : wdt2pow17
2**17 clock cycles.
15 : wdt2pow16
2**16 clock cycles.
End of enumeration elements list.
CLKRDY_IE : Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock.
bits : 27 - 27 (1 bit)
CLKRDY : Clock Status.
bits : 28 - 28 (1 bit)
WIN_EN : Enables the Windowed Watchdog Function.
bits : 29 - 29 (1 bit)
Enumeration:
0 : dis
Windowed Mode Disabled (i.e. Compatibility Mode).
1 : en
Windowed Mode Enabled.
End of enumeration elements list.
RST_EARLY : Windowed Watchdog Timer Reset Flag Too Soon.
bits : 30 - 30 (1 bit)
Enumeration: ( read-write )
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
RST_LATE : Windowed Watchdog Timer Reset Flag Too Late.
bits : 31 - 31 (1 bit)
Enumeration: ( read-write )
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
Windowed Watchdog Timer Reset Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RESET : Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled.
bits : 0 - 7 (8 bit)
Enumeration:
0x000000A5 : seq0
The first value to be written to reset the WDT.
0x0000005A : seq1
The second value to be written to reset the WDT.
End of enumeration elements list.
Windowed Watchdog Timer Clock Select Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : WWDT Clock Selection Register.
bits : 0 - 2 (3 bit)
Windowed Watchdog Timer Count Register.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COUNT : Current Value of the Windowed Watchdog Timer Counter.
bits : 0 - 31 (32 bit)
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