\n

QDEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL

INITIAL

COMPARE

INDEX

CAPTURE

STATUS

POSITION

CAPDLY

INTFL

INTEN

MAXCNT


CTRL

Control Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 en mode swap filter rst_index rst_maxcnt sticky psc

en :
bits : 0 - 0 (1 bit)
access : read-write

Enumeration: enum

0x0 : disable


0x1 : enable


End of enumeration elements list.

mode :
bits : 1 - 2 (2 bit)
access : read-write

Enumeration: enum

0 : x1mode


1 : x2mode


2 : x4mode


End of enumeration elements list.

swap :
bits : 3 - 3 (1 bit)
access : read-write

filter :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration: enum

0 : 1_sample


1 : 2_samples


2 : 3_samples


3 : 4_samples


End of enumeration elements list.

rst_index :
bits : 6 - 6 (1 bit)
access : read-write

rst_maxcnt :
bits : 7 - 7 (1 bit)
access : read-write

sticky :
bits : 8 - 8 (1 bit)
access : read-write

psc :
bits : 16 - 18 (3 bit)
access : read-write

Enumeration: enum

0 : div1


1 : div2


2 : div4


3 : div8


4 : div16


5 : div32


6 : div64


7 : div128


End of enumeration elements list.


INITIAL

Initial Count Register.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INITIAL INITIAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 initial

initial :
bits : 0 - 31 (32 bit)
access : read-write


COMPARE

Compare Register.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMPARE COMPARE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 compare

compare :
bits : 0 - 31 (32 bit)
access : read-write


INDEX

Index Register. count captured when QEI fired
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INDEX INDEX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 index

index :
bits : 0 - 31 (32 bit)
access : read-only


CAPTURE

Capture Register. counter captured when QES fired
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPTURE CAPTURE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 capture

capture :
bits : 0 - 31 (32 bit)
access : read-only


STATUS

Status Register.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dir

dir :
bits : 0 - 0 (1 bit)
access : read-only


POSITION

Count Register. raw counter value
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

POSITION POSITION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 position

position :
bits : 0 - 31 (32 bit)
access : read-only


CAPDLY

delay CAPTURE
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPDLY CAPDLY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 capdly

capdly :
bits : 0 - 31 (32 bit)
access : read-write


INTFL

Interrupt Flag Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTFL INTFL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 index qerr compare maxcnt capture dir move

index :
bits : 0 - 0 (1 bit)
access : read-write

qerr :
bits : 1 - 1 (1 bit)
access : read-write

compare :
bits : 2 - 2 (1 bit)
access : read-write

maxcnt :
bits : 3 - 3 (1 bit)
access : read-write

capture :
bits : 4 - 4 (1 bit)
access : read-write

dir :
bits : 5 - 5 (1 bit)
access : read-write

move :
bits : 6 - 6 (1 bit)
access : read-write


INTEN

Interrupt Enable Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 index qerr compare maxcnt capture dir move

index :
bits : 0 - 0 (1 bit)
access : read-write

qerr :
bits : 1 - 1 (1 bit)
access : read-write

compare :
bits : 2 - 2 (1 bit)
access : read-write

maxcnt :
bits : 3 - 3 (1 bit)
access : read-write

capture :
bits : 4 - 4 (1 bit)
access : read-write

dir :
bits : 5 - 5 (1 bit)
access : read-write

move :
bits : 6 - 6 (1 bit)
access : read-write


MAXCNT

Maximum Count Register.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MAXCNT MAXCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 maxcnt

maxcnt :
bits : 0 - 31 (32 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.