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SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

CFGR

PCFGR

CLK_CFGR0

CLK_CFGR1

CLK_CFGR2

CLK_OUT_CR

CLK_GATE_KEY

CLK_GATE_CR0

CLK_GATE_CR1

CLK_GATE_CR2

CLK_GATE_VFREG_CR

CLK_PP_CR

CLK_CALIB_KEY

CLK_CALIB_HIRC

RST_SYS_CS

RST_SYS_CSR

RST_COMM_CR

DBG_DEVID

DBG_CSR

DBG_EBKP

PWR_CR

SYSHOLD_CSR


CFGR

SYSCFG_CFGR
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REMAP_MODER

REMAP_MODER : Memory mapping selection bits
bits : 0 - 2 (3 bit)
access : read-write


PCFGR

SYSCFG_PCFGR
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCFGR PCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM1_SLEP_RUN PWM2_SLEP_RUN PWM3_SLEP_RUN

PWM1_SLEP_RUN : PWM1 run control when the CPU enters Sleep0
bits : 0 - 0 (1 bit)
access : read-write

PWM2_SLEP_RUN : PWM2 run control when the CPU enters Sleep0
bits : 1 - 2 (2 bit)
access : read-write

PWM3_SLEP_RUN : PWM3 run control when the CPU enters Sleep0
bits : 2 - 4 (3 bit)
access : read-write


CLK_CFGR0

CLK_CFGR0
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CFGR0 CLK_CFGR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRC_FREQ_SEL

HIRC_FREQ_SEL : HIRC frequency selection
bits : 0 - 1 (2 bit)
access : read-write


CLK_CFGR1

CLK_CFGR1
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CFGR1 CLK_CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCLK_SEL

SCLK_SEL : High frequency clock source selection
bits : 0 - 1 (2 bit)
access : read-write


CLK_CFGR2

CLK_CFGR2
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CFGR2 CLK_CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_DIV HIRC_DIV PCLK_DIV TPCLK_DIV

HCLK_DIV : High frequency clock clock divide
bits : 0 - 2 (3 bit)
access : read-write

HIRC_DIV : High internal RC oscillator clock divide
bits : 8 - 18 (11 bit)
access : read-write

PCLK_DIV : Peripherals clock divide
bits : 16 - 32 (17 bit)
access : read-write

TPCLK_DIV : TP clock divide
bits : 24 - 50 (27 bit)
access : read-write


CLK_OUT_CR

CLK_OUT_CR
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_OUT_CR CLK_OUT_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OCLK_SOURCE1 OCLK_SOURCE1_EN OCLK_SOURCE2 OCLK_SOURCE2_EN OCLK_DIV1 OCLK_DIV2

OCLK_SOURCE1 : Output clock source selection for CLKO_1
bits : 0 - 4 (5 bit)
access : read-write

OCLK_SOURCE1_EN : OCLK_SOURCE1 output control
bits : 7 - 14 (8 bit)
access : read-write

OCLK_SOURCE2 : Output clock divide 2
bits : 8 - 20 (13 bit)
access : read-write

OCLK_SOURCE2_EN : OCLK_SOURCE2 output control
bits : 15 - 30 (16 bit)
access : read-write

OCLK_DIV1 : Output clock divide 1
bits : 16 - 39 (24 bit)
access : read-write

OCLK_DIV2 : Output clock divide 2
bits : 24 - 55 (32 bit)
access : read-write


CLK_GATE_KEY

CLK_GATE_KEY
address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GATE_KEY CLK_GATE_KEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_GATE_KEY

CLK_GATE_KEY : Clock gating key
bits : 0 - 15 (16 bit)
access : read-write


CLK_GATE_CR0

CLK_GATE_CR0
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GATE_CR0 CLK_GATE_CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_GATE_SET CLK_GATE_CLR

CLK_GATE_SET : Set by software to set all gating clock bits
bits : 30 - 60 (31 bit)
access : read-write

CLK_GATE_CLR : Set by software to clear all gating clock bits
bits : 31 - 62 (32 bit)
access : read-write


CLK_GATE_CR1

CLK_GATE_CR1
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GATE_CR1 CLK_GATE_CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKG_GPIOA HCLKG_GPIOB HCLKG_GPIOC PCLKG_IWDG PCLKG_TP PCLKG_AIP

HCLKG_GPIOA : Gating GPIOA clock
bits : 0 - 0 (1 bit)
access : read-write

HCLKG_GPIOB : Gating GPIOB clock
bits : 1 - 2 (2 bit)
access : read-write

HCLKG_GPIOC : Gating GPIOC clock
bits : 2 - 4 (3 bit)
access : read-write

PCLKG_IWDG : Gating independent watchdog clock
bits : 8 - 16 (9 bit)
access : read-write

PCLKG_TP : Gating TP clock
bits : 9 - 18 (10 bit)
access : read-write

PCLKG_AIP : Gating AIP clock
bits : 16 - 32 (17 bit)
access : read-write


CLK_GATE_CR2

CLK_GATE_CR2
address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GATE_CR2 CLK_GATE_CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCLKG_UART PCLKG_USART PCLKG_I2C PCLKG_TC1 PCLKG_TC2 PCLKG_PWM1 PCLKG_PWM2 PCLKG_PWM3 PCLKG_EINT

PCLKG_UART : Gating UART clock
bits : 0 - 0 (1 bit)
access : read-write

PCLKG_USART : Gating USART clock
bits : 1 - 2 (2 bit)
access : read-write

PCLKG_I2C : Gating I2C clock
bits : 2 - 4 (3 bit)
access : read-write

PCLKG_TC1 : Gating TC1 clock
bits : 8 - 16 (9 bit)
access : read-write

PCLKG_TC2 : Gating TC2 clock
bits : 9 - 18 (10 bit)
access : read-write

PCLKG_PWM1 : Gating PWM1 clock
bits : 16 - 32 (17 bit)
access : read-write

PCLKG_PWM2 : Gating PWM2 clock
bits : 17 - 34 (18 bit)
access : read-write

PCLKG_PWM3 : Gating PWM3 clock
bits : 18 - 36 (19 bit)
access : read-write

PCLKG_EINT : Gating EINT clock
bits : 24 - 48 (25 bit)
access : read-write


CLK_GATE_VFREG_CR

CLK_GATE_VFREG_CR
address_offset : 0x15C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GATE_VFREG_CR CLK_GATE_VFREG_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFREG_CLK

VFREG_CLK : Gating VERIFYSET register clock
bits : 0 - 0 (1 bit)
access : read-write


CLK_PP_CR

CLK_PP_CR
address_offset : 0x160 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PP_CR CLK_PP_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER1_ECSS TIMER1CLK_DIV TIMER2_ECSS TIMER2CLK_DIV

TIMER1_ECSS : External clock source selection
bits : 0 - 1 (2 bit)
access : read-write

TIMER1CLK_DIV : Timer external clock divide
bits : 4 - 10 (7 bit)
access : read-write

TIMER2_ECSS : External clock source selection
bits : 8 - 17 (10 bit)
access : read-write

TIMER2CLK_DIV : Timer external clock divide
bits : 12 - 26 (15 bit)
access : read-write


CLK_CALIB_KEY

CLK_CALIB_KEY
address_offset : 0x190 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CALIB_KEY CLK_CALIB_KEY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_CALIB_KEY

CLK_CALIB_KEY : Clock calibration key
bits : 0 - 15 (16 bit)
access : read-write


CLK_CALIB_HIRC

CLK_CALIB_HIRC
address_offset : 0x194 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CALIB_HIRC CLK_CALIB_HIRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRC_RT

HIRC_RT : Trim bits of Main frequency IRC
bits : 0 - 7 (8 bit)
access : read-write


RST_SYS_CS

RST_SYS_CS
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RST_SYS_CS RST_SYS_CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW_RST

SW_RST : Sofware reset
bits : 0 - 0 (1 bit)
access : read-write


RST_SYS_CSR

RST_SYS_CSR
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RST_SYS_CSR RST_SYS_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDG_RSTF SFT_RSTF POR_RSTF PIN_RSTF LVR_RSTF CHIPPT_RSTF RMVF

IWDG_RSTF : Watchdog reset flag
bits : 0 - 0 (1 bit)
access : read-write

SFT_RSTF : Software reset flag
bits : 1 - 2 (2 bit)
access : read-write

POR_RSTF : POR reset flag
bits : 2 - 4 (3 bit)
access : read-write

PIN_RSTF : PIN reset flag
bits : 3 - 6 (4 bit)
access : read-write

LVR_RSTF : LVR reset flag
bits : 4 - 8 (5 bit)
access : read-write

CHIPPT_RSTF : CHIPPT reset flag
bits : 8 - 16 (9 bit)
access : read-write

RMVF : Remove reset flag
bits : 31 - 62 (32 bit)
access : read-write


RST_COMM_CR

RST_COMM_CR
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RST_COMM_CR RST_COMM_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_RST USART_RST I2C_RST

UART_RST : UART reset bit
bits : 0 - 0 (1 bit)
access : read-write

USART_RST : USART reset bit
bits : 1 - 2 (2 bit)
access : read-write

I2C_RST : I2C reset bit
bits : 2 - 4 (3 bit)
access : read-write


DBG_DEVID

DBG_DEVID
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_DEVID DBG_DEVID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Product_Number Process Storage Marker Product_Type

Product_Number : Product_Number
bits : 0 - 15 (16 bit)
access : read-write

Process : Process
bits : 16 - 36 (21 bit)
access : read-write

Storage : Storage
bits : 21 - 44 (24 bit)
access : read-write

Marker : Marker
bits : 24 - 51 (28 bit)
access : read-write

Product_Type : Product_Type
bits : 28 - 59 (32 bit)
access : read-write


DBG_CSR

DBG_CSR
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_CSR DBG_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWR_MODER_ST

PWR_MODER_ST : Power mode status
bits : 8 - 17 (10 bit)
access : read-write


DBG_EBKP

DBG_EBKP
address_offset : 0x340 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_EBKP DBG_EBKP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBKP_COUNT EBKPT_OVF

EBKP_COUNT : Expand breakpoint register counter
bits : 0 - 4 (5 bit)
access : read-write

EBKPT_OVF : Expand breakpoint register overflow flag
bits : 8 - 16 (9 bit)
access : read-write


PWR_CR

SYSCFG_PWR_CR
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR_CR PWR_CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYS_REGMOD_SLEP

SYS_REGMOD_SLEP : System regulator mode in sleep0
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : Idle

System regulator at idle mode when entry sleep0

1 : Green

System regulator at green mode when entry sleep0

End of enumeration elements list.


SYSHOLD_CSR

SYSHOLD_CSR
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSHOLD_CSR SYSHOLD_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHSF

SHSF : System hold status flag
bits : 0 - 0 (1 bit)
access : read-write



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