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USBCTRL_DPRAM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

SETUP_PACKET_LOW

EP2_IN_CONTROL

EP2_OUT_CONTROL

EP3_IN_CONTROL

EP3_OUT_CONTROL

EP4_IN_CONTROL

EP4_OUT_CONTROL

EP5_IN_CONTROL

EP5_OUT_CONTROL

EP6_IN_CONTROL

EP6_OUT_CONTROL

EP7_IN_CONTROL

EP7_OUT_CONTROL

SETUP_PACKET_HIGH

EP8_IN_CONTROL

EP8_OUT_CONTROL

EP9_IN_CONTROL

EP9_OUT_CONTROL

EP10_IN_CONTROL

EP10_OUT_CONTROL

EP11_IN_CONTROL

EP11_OUT_CONTROL

EP12_IN_CONTROL

EP12_OUT_CONTROL

EP13_IN_CONTROL

EP13_OUT_CONTROL

EP14_IN_CONTROL

EP14_OUT_CONTROL

EP15_IN_CONTROL

EP15_OUT_CONTROL

EP1_IN_CONTROL

EP0_IN_BUFFER_CONTROL

EP0_OUT_BUFFER_CONTROL

EP1_IN_BUFFER_CONTROL

EP1_OUT_BUFFER_CONTROL

EP2_IN_BUFFER_CONTROL

EP2_OUT_BUFFER_CONTROL

EP3_IN_BUFFER_CONTROL

EP3_OUT_BUFFER_CONTROL

EP4_IN_BUFFER_CONTROL

EP4_OUT_BUFFER_CONTROL

EP5_IN_BUFFER_CONTROL

EP5_OUT_BUFFER_CONTROL

EP6_IN_BUFFER_CONTROL

EP6_OUT_BUFFER_CONTROL

EP7_IN_BUFFER_CONTROL

EP7_OUT_BUFFER_CONTROL

EP1_OUT_CONTROL

EP8_IN_BUFFER_CONTROL

EP8_OUT_BUFFER_CONTROL

EP9_IN_BUFFER_CONTROL

EP9_OUT_BUFFER_CONTROL

EP10_IN_BUFFER_CONTROL

EP10_OUT_BUFFER_CONTROL

EP11_IN_BUFFER_CONTROL

EP11_OUT_BUFFER_CONTROL

EP12_IN_BUFFER_CONTROL

EP12_OUT_BUFFER_CONTROL

EP13_IN_BUFFER_CONTROL

EP13_OUT_BUFFER_CONTROL

EP14_IN_BUFFER_CONTROL

EP14_OUT_BUFFER_CONTROL

EP15_IN_BUFFER_CONTROL

EP15_OUT_BUFFER_CONTROL


SETUP_PACKET_LOW

Bytes 0-3 of the SETUP packet from the host.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
reset_value : 0x0

SETUP_PACKET_LOW SETUP_PACKET_LOW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMREQUESTTYPE BREQUEST WVALUE

BMREQUESTTYPE :
bits : 0 - 7 (8 bit)
access : read-write

BREQUEST :
bits : 8 - 15 (8 bit)
access : read-write

WVALUE :
bits : 16 - 31 (16 bit)
access : read-write


EP2_IN_CONTROL


address_offset : 0x10 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP2_IN_CONTROL EP2_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP2_OUT_CONTROL


address_offset : 0x14 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP2_OUT_CONTROL EP2_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP3_IN_CONTROL


address_offset : 0x18 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP3_IN_CONTROL EP3_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP3_OUT_CONTROL


address_offset : 0x1C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP3_OUT_CONTROL EP3_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP4_IN_CONTROL


address_offset : 0x20 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP4_IN_CONTROL EP4_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP4_OUT_CONTROL


address_offset : 0x24 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP4_OUT_CONTROL EP4_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP5_IN_CONTROL


address_offset : 0x28 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP5_IN_CONTROL EP5_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP5_OUT_CONTROL


address_offset : 0x2C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP5_OUT_CONTROL EP5_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP6_IN_CONTROL


address_offset : 0x30 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP6_IN_CONTROL EP6_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP6_OUT_CONTROL


address_offset : 0x34 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP6_OUT_CONTROL EP6_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP7_IN_CONTROL


address_offset : 0x38 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP7_IN_CONTROL EP7_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP7_OUT_CONTROL


address_offset : 0x3C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP7_OUT_CONTROL EP7_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


SETUP_PACKET_HIGH

Bytes 4-7 of the setup packet from the host.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
reset_value : 0x0

SETUP_PACKET_HIGH SETUP_PACKET_HIGH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINDEX WLENGTH

WINDEX :
bits : 0 - 15 (16 bit)
access : read-write

WLENGTH :
bits : 16 - 31 (16 bit)
access : read-write


EP8_IN_CONTROL


address_offset : 0x40 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP8_IN_CONTROL EP8_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP8_OUT_CONTROL


address_offset : 0x44 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP8_OUT_CONTROL EP8_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP9_IN_CONTROL


address_offset : 0x48 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP9_IN_CONTROL EP9_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP9_OUT_CONTROL


address_offset : 0x4C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP9_OUT_CONTROL EP9_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP10_IN_CONTROL


address_offset : 0x50 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP10_IN_CONTROL EP10_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP10_OUT_CONTROL


address_offset : 0x54 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP10_OUT_CONTROL EP10_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP11_IN_CONTROL


address_offset : 0x58 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP11_IN_CONTROL EP11_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP11_OUT_CONTROL


address_offset : 0x5C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP11_OUT_CONTROL EP11_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP12_IN_CONTROL


address_offset : 0x60 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP12_IN_CONTROL EP12_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP12_OUT_CONTROL


address_offset : 0x64 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP12_OUT_CONTROL EP12_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP13_IN_CONTROL


address_offset : 0x68 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP13_IN_CONTROL EP13_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP13_OUT_CONTROL


address_offset : 0x6C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP13_OUT_CONTROL EP13_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP14_IN_CONTROL


address_offset : 0x70 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP14_IN_CONTROL EP14_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP14_OUT_CONTROL


address_offset : 0x74 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP14_OUT_CONTROL EP14_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP15_IN_CONTROL


address_offset : 0x78 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP15_IN_CONTROL EP15_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP15_OUT_CONTROL


address_offset : 0x7C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP15_OUT_CONTROL EP15_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP1_IN_CONTROL


address_offset : 0x8 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP1_IN_CONTROL EP1_IN_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP0_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP0_IN_BUFFER_CONTROL EP0_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP0_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP0_OUT_BUFFER_CONTROL EP0_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP1_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP1_IN_BUFFER_CONTROL EP1_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP1_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP1_OUT_BUFFER_CONTROL EP1_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP2_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP2_IN_BUFFER_CONTROL EP2_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP2_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP2_OUT_BUFFER_CONTROL EP2_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP3_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP3_IN_BUFFER_CONTROL EP3_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP3_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP3_OUT_BUFFER_CONTROL EP3_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP4_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP4_IN_BUFFER_CONTROL EP4_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP4_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP4_OUT_BUFFER_CONTROL EP4_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP5_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP5_IN_BUFFER_CONTROL EP5_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP5_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP5_OUT_BUFFER_CONTROL EP5_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP6_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP6_IN_BUFFER_CONTROL EP6_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP6_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP6_OUT_BUFFER_CONTROL EP6_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP7_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP7_IN_BUFFER_CONTROL EP7_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP7_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP7_OUT_BUFFER_CONTROL EP7_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP1_OUT_CONTROL


address_offset : 0xC Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP1_OUT_CONTROL EP1_OUT_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFFER_ADDRESS INTERRUPT_ON_NAK INTERRUPT_ON_STALL ENDPOINT_TYPE INTERRUPT_PER_DOUBLE_BUFF INTERRUPT_PER_BUFF DOUBLE_BUFFERED ENABLE

BUFFER_ADDRESS : 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
bits : 0 - 15 (16 bit)
access : read-write

INTERRUPT_ON_NAK : Trigger an interrupt if a NAK is sent. Intended for debug only.
bits : 16 - 16 (1 bit)
access : read-write

INTERRUPT_ON_STALL : Trigger an interrupt if a STALL is sent. Intended for debug only.
bits : 17 - 17 (1 bit)
access : read-write

ENDPOINT_TYPE :
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Control


1 : Isochronous


2 : Bulk


3 : Interrupt


End of enumeration elements list.

INTERRUPT_PER_DOUBLE_BUFF : Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
bits : 28 - 28 (1 bit)
access : read-write

INTERRUPT_PER_BUFF : Trigger an interrupt each time a buffer is done.
bits : 29 - 29 (1 bit)
access : read-write

DOUBLE_BUFFERED : This endpoint is double buffered.
bits : 30 - 30 (1 bit)
access : read-write

ENABLE : Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
bits : 31 - 31 (1 bit)
access : read-write


EP8_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP8_IN_BUFFER_CONTROL EP8_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP8_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP8_OUT_BUFFER_CONTROL EP8_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP9_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP9_IN_BUFFER_CONTROL EP9_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP9_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP9_OUT_BUFFER_CONTROL EP9_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP10_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP10_IN_BUFFER_CONTROL EP10_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP10_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP10_OUT_BUFFER_CONTROL EP10_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP11_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP11_IN_BUFFER_CONTROL EP11_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP11_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xDC Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP11_OUT_BUFFER_CONTROL EP11_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP12_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP12_IN_BUFFER_CONTROL EP12_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP12_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP12_OUT_BUFFER_CONTROL EP12_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP13_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP13_IN_BUFFER_CONTROL EP13_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP13_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xEC Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP13_OUT_BUFFER_CONTROL EP13_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP14_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP14_IN_BUFFER_CONTROL EP14_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP14_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP14_OUT_BUFFER_CONTROL EP14_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP15_IN_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP15_IN_BUFFER_CONTROL EP15_IN_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write


EP15_OUT_BUFFER_CONTROL

Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
address_offset : 0xFC Bytes (0x0)
size : 32 bit
reset_value : 0x0

EP15_OUT_BUFFER_CONTROL EP15_OUT_BUFFER_CONTROL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH_0 AVAILABLE_0 STALL RESET PID_0 LAST_0 FULL_0 LENGTH_1 AVAILABLE_1 DOUBLE_BUFFER_ISO_OFFSET PID_1 LAST_1 FULL_1

LENGTH_0 : The length of the data in buffer 0.
bits : 0 - 9 (10 bit)
access : read-write

AVAILABLE_0 : Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 10 - 10 (1 bit)
access : read-write

STALL : Reply with a stall (valid for both buffers).
bits : 11 - 11 (1 bit)
access : read-write

RESET : Reset the buffer selector to buffer 0.
bits : 12 - 12 (1 bit)
access : read-write

PID_0 : The data pid of buffer 0.
bits : 13 - 13 (1 bit)
access : read-write

LAST_0 : Buffer 0 is the last buffer of the transfer.
bits : 14 - 14 (1 bit)
access : read-write

FULL_0 : Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 15 - 15 (1 bit)
access : read-write

LENGTH_1 : The length of the data in buffer 1.
bits : 16 - 25 (10 bit)
access : read-write

AVAILABLE_1 : Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
bits : 26 - 26 (1 bit)
access : read-write

DOUBLE_BUFFER_ISO_OFFSET : The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes.
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

0 : 128


1 : 256


2 : 512


3 : 1024


End of enumeration elements list.

PID_1 : The data pid of buffer 1.
bits : 29 - 29 (1 bit)
access : read-write

LAST_1 : Buffer 1 is the last buffer of the transfer.
bits : 30 - 30 (1 bit)
access : read-write

FULL_1 : Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
bits : 31 - 31 (1 bit)
access : read-write



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