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PWR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTLR

AWUPSC

CSR

AWUCSR

AWUWR


CTLR

Power control register (PWR_CTRL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDDS PVDE PLS

PDDS : Power Down Deep Sleep
bits : 1 - 1 (1 bit)

PVDE : Power Voltage Detector Enable
bits : 4 - 4 (1 bit)

PLS : PVD Level Selection
bits : 5 - 7 (3 bit)


AWUPSC

Automatic wake-up prescaler register (PWR_AWUPSC)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

AWUPSC AWUPSC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWUPSC

AWUPSC : Wake-up prescaler
bits : 0 - 3 (4 bit)
access : read-write


CSR

Power control state register (PWR_CSR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

CSR CSR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PVDO

PVDO : PVD Output
bits : 2 - 2 (1 bit)
access : read-only


AWUCSR

Automatic wake-up control state register (PWR_AWUCSR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

AWUCSR AWUCSR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWUEN

AWUEN : Automatic wake-up enable
bits : 1 - 1 (1 bit)
access : read-write


AWUWR

Automatic wake window comparison value register (PWR_AWUWR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

AWUWR AWUWR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWUWR

AWUWR : AWU window value
bits : 0 - 5 (6 bit)
access : read-write



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