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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTLR

APB1PRSTR

AHBPCENR

APB2PCENR

APB1PCENR

RSTSCKR

CFGR0

INTR

APB2PRSTR


CTLR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSION HSIRDY HSITRIM HSICAL HSEON HSERDY HSEBYP CSSON PLLON PLLRDY

HSION : Internal High Speed clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSIRDY : Internal High Speed clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSITRIM : Internal High Speed clock trimming
bits : 3 - 7 (5 bit)
access : read-write

HSICAL : Internal High Speed clock Calibration
bits : 8 - 15 (8 bit)
access : read-only

HSEON : External High Speed clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : External High Speed clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : External High Speed clock Bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSON : Clock Security System enable
bits : 19 - 19 (1 bit)
access : read-write

PLLON : PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


APB1PRSTR

PB1 peripheral reset register (RCC_APB1PRSTR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1PRSTR APB1PRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST WWDGRST I2C1RST PWRRST

TIM2RST : TIM2 reset
bits : 0 - 0 (1 bit)

WWDGRST : Window watchdog reset
bits : 11 - 11 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)


AHBPCENR

HB Peripheral Clock enable register (RCC_AHBPCENR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBPCENR AHBPCENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA1EN SRAMEN

DMA1EN : DMA clock enable
bits : 0 - 0 (1 bit)

SRAMEN : SRAM interface clock enable
bits : 2 - 2 (1 bit)


APB2PCENR

PB2 peripheral clock enable register (RCC_APB2PCENR)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2PCENR APB2PCENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIOEN IOPAEN IOPCEN IOPDEN ADC1EN TIM1EN SPI1EN USART1EN

AFIOEN : Alternate function I/O clock enable
bits : 0 - 0 (1 bit)

IOPAEN : I/O port A clock enable
bits : 2 - 2 (1 bit)

IOPCEN : I/O port C clock enable
bits : 4 - 4 (1 bit)

IOPDEN : I/O port D clock enable
bits : 5 - 5 (1 bit)

ADC1EN : ADC1 interface clock enable
bits : 9 - 9 (1 bit)

TIM1EN : TIM1 Timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI 1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : USART1 clock enable
bits : 14 - 14 (1 bit)


APB1PCENR

PB1 peripheral clock enable register (RCC_APB1PCENR)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1PCENR APB1PCENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN WWDGEN I2C1EN PWREN

TIM2EN : Timer 2 clock enable
bits : 0 - 0 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

I2C1EN : I2C 1 clock enable
bits : 21 - 21 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)


RSTSCKR

Control/status register (RCC_RSTSCKR)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

RSTSCKR RSTSCKR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY RMVF PINRSTF PORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRRSTF

LSION : Internal low speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : Internal low speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

PINRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-only

PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-only

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-only

IWDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-only

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-only

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-only


CFGR0

Clock configuration register (RCC_CFGR0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

CFGR0 CFGR0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE ADCPRE PLLSRC MCO

SW : System clock Switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System Clock Switch Status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : HB prescaler
bits : 4 - 7 (4 bit)
access : read-write

ADCPRE : ADC prescaler
bits : 11 - 15 (5 bit)
access : read-write

PLLSRC : PLL entry clock source
bits : 16 - 16 (1 bit)
access : read-write

MCO : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write


INTR

Clock interrupt register (RCC_INTR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

INTR INTR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF HSIRDYF HSERDYF PLLRDYF CSSF LSIRDYIE HSIRDYIE HSERDYIE PLLRDYIE LSIRDYC HSIRDYC HSERDYC PLLRDYC CSSC

LSIRDYF : LSI Ready Interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

HSIRDYF : HSI Ready Interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HSERDYF : HSE Ready Interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYF : PLL Ready Interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

CSSF : Clock Security System Interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

LSIRDYIE : LSI Ready Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

HSIRDYIE : HSI Ready Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

HSERDYIE : HSE Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : PLL Ready Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

LSIRDYC : LSI Ready Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only

HSIRDYC : HSI Ready Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only

HSERDYC : HSE Ready Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : PLL Ready Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only

CSSC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only


APB2PRSTR

PB2 peripheral reset register (RCC_APB2PRSTR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2PRSTR APB2PRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIORST IOPARST IOPCRST IOPDRST ADC1RST TIM1RST SPI1RST USART1RST

AFIORST : Alternate function I/O reset
bits : 0 - 0 (1 bit)

IOPARST : IO port A reset
bits : 2 - 2 (1 bit)

IOPCRST : IO port C reset
bits : 4 - 4 (1 bit)

IOPDRST : IO port D reset
bits : 5 - 5 (1 bit)

ADC1RST : ADC 1 interface reset
bits : 9 - 9 (1 bit)

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)



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