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GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFGLR

BSHR

BCR

LCKR

INDR

OUTDR


CFGLR

Port configuration register low (GPIOn_CFGLR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGLR CFGLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE0 CNF0 MODE1 CNF1 MODE2 CNF2 MODE3 CNF3 MODE4 CNF4 MODE5 CNF5 MODE6 CNF6 MODE7 CNF7

MODE0 : Port n.0 mode bits
bits : 0 - 1 (2 bit)

CNF0 : Port n.0 configuration bits
bits : 2 - 3 (2 bit)

MODE1 : Port n.1 mode bits
bits : 4 - 5 (2 bit)

CNF1 : Port n.1 configuration bits
bits : 6 - 7 (2 bit)

MODE2 : Port n.2 mode bits
bits : 8 - 9 (2 bit)

CNF2 : Port n.2 configuration bits
bits : 10 - 11 (2 bit)

MODE3 : Port n.3 mode bits
bits : 12 - 13 (2 bit)

CNF3 : Port n.3 configuration bits
bits : 14 - 15 (2 bit)

MODE4 : Port n.4 mode bits
bits : 16 - 17 (2 bit)

CNF4 : Port n.4 configuration bits
bits : 18 - 19 (2 bit)

MODE5 : Port n.5 mode bits
bits : 20 - 21 (2 bit)

CNF5 : Port n.5 configuration bits
bits : 22 - 23 (2 bit)

MODE6 : Port n.6 mode bits
bits : 24 - 25 (2 bit)

CNF6 : Port n.6 configuration bits
bits : 26 - 27 (2 bit)

MODE7 : Port n.7 mode bits
bits : 28 - 29 (2 bit)

CNF7 : Port n.7 configuration bits
bits : 30 - 31 (2 bit)


BSHR

Port bit set/reset register (GPIOn_BSHR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BSHR BSHR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BS0 BS1 BS2 BS3 BS4 BS5 BS6 BS7 BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7

BS0 : Set bit 0
bits : 0 - 0 (1 bit)

BS1 : Set bit 1
bits : 1 - 1 (1 bit)

BS2 : Set bit 1
bits : 2 - 2 (1 bit)

BS3 : Set bit 3
bits : 3 - 3 (1 bit)

BS4 : Set bit 4
bits : 4 - 4 (1 bit)

BS5 : Set bit 5
bits : 5 - 5 (1 bit)

BS6 : Set bit 6
bits : 6 - 6 (1 bit)

BS7 : Set bit 7
bits : 7 - 7 (1 bit)

BR0 : Reset bit 0
bits : 16 - 16 (1 bit)

BR1 : Reset bit 1
bits : 17 - 17 (1 bit)

BR2 : Reset bit 2
bits : 18 - 18 (1 bit)

BR3 : Reset bit 3
bits : 19 - 19 (1 bit)

BR4 : Reset bit 4
bits : 20 - 20 (1 bit)

BR5 : Reset bit 5
bits : 21 - 21 (1 bit)

BR6 : Reset bit 6
bits : 22 - 22 (1 bit)

BR7 : Reset bit 7
bits : 23 - 23 (1 bit)


BCR

Port bit reset register (GPIOn_BCR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BCR BCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR0 BR1 BR2 BR3 BR4 BR5 BR6 BR7

BR0 : Reset bit 0
bits : 0 - 0 (1 bit)

BR1 : Reset bit 1
bits : 1 - 1 (1 bit)

BR2 : Reset bit 1
bits : 2 - 2 (1 bit)

BR3 : Reset bit 3
bits : 3 - 3 (1 bit)

BR4 : Reset bit 4
bits : 4 - 4 (1 bit)

BR5 : Reset bit 5
bits : 5 - 5 (1 bit)

BR6 : Reset bit 6
bits : 6 - 6 (1 bit)

BR7 : Reset bit 7
bits : 7 - 7 (1 bit)


LCKR

Port configuration lock register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LCKR LCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCK0 LCK1 LCK2 LCK3 LCK4 LCK5 LCK6 LCK7 LCKK

LCK0 : Port A Lock bit 0
bits : 0 - 0 (1 bit)

LCK1 : Port A Lock bit 1
bits : 1 - 1 (1 bit)

LCK2 : Port A Lock bit 2
bits : 2 - 2 (1 bit)

LCK3 : Port A Lock bit 3
bits : 3 - 3 (1 bit)

LCK4 : Port A Lock bit 4
bits : 4 - 4 (1 bit)

LCK5 : Port A Lock bit 5
bits : 5 - 5 (1 bit)

LCK6 : Port A Lock bit 6
bits : 6 - 6 (1 bit)

LCK7 : Port A Lock bit 7
bits : 7 - 7 (1 bit)

LCKK : Lock key
bits : 8 - 8 (1 bit)


INDR

Port input data register (GPIOn_INDR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INDR INDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDR0 IDR1 IDR2 IDR3 IDR4 IDR5 IDR6 IDR7

IDR0 : Port input data
bits : 0 - 0 (1 bit)

IDR1 : Port input data
bits : 1 - 1 (1 bit)

IDR2 : Port input data
bits : 2 - 2 (1 bit)

IDR3 : Port input data
bits : 3 - 3 (1 bit)

IDR4 : Port input data
bits : 4 - 4 (1 bit)

IDR5 : Port input data
bits : 5 - 5 (1 bit)

IDR6 : Port input data
bits : 6 - 6 (1 bit)

IDR7 : Port input data
bits : 7 - 7 (1 bit)


OUTDR

Port output data register (GPIOn_OUTDR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTDR OUTDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODR0 ODR1 ODR2 ODR3 ODR4 ODR5 ODR6 ODR7

ODR0 : Port output data
bits : 0 - 0 (1 bit)

ODR1 : Port output data
bits : 1 - 1 (1 bit)

ODR2 : Port output data
bits : 2 - 2 (1 bit)

ODR3 : Port output data
bits : 3 - 3 (1 bit)

ODR4 : Port output data
bits : 4 - 4 (1 bit)

ODR5 : Port output data
bits : 5 - 5 (1 bit)

ODR6 : Port output data
bits : 6 - 6 (1 bit)

ODR7 : Port output data
bits : 7 - 7 (1 bit)



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