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EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INTENR

SWIEVR

INTFR

EVENR

RTENR

FTENR


INTENR

Interrupt mask register (EXTI_INTENR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENR INTENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0 MR1 MR2 MR3 MR4 MR5 MR6 MR7 MR8 MR9

MR0 : Interrupt Mask on line 0
bits : 0 - 0 (1 bit)

MR1 : Interrupt Mask on line 1
bits : 1 - 1 (1 bit)

MR2 : Interrupt Mask on line 2
bits : 2 - 2 (1 bit)

MR3 : Interrupt Mask on line 3
bits : 3 - 3 (1 bit)

MR4 : Interrupt Mask on line 4
bits : 4 - 4 (1 bit)

MR5 : Interrupt Mask on line 5
bits : 5 - 5 (1 bit)

MR6 : Interrupt Mask on line 6
bits : 6 - 6 (1 bit)

MR7 : Interrupt Mask on line 7
bits : 7 - 7 (1 bit)

MR8 : Interrupt Mask on line 8
bits : 8 - 8 (1 bit)

MR9 : Interrupt Mask on line 9
bits : 9 - 9 (1 bit)


SWIEVR

Software interrupt event register (EXTI_SWIEVR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWIEVR SWIEVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWIER0 SWIER1 SWIER2 SWIER3 SWIER4 SWIER5 SWIER6 SWIER7 SWIER8 SWIER9

SWIER0 : Software Interrupt on line 0
bits : 0 - 0 (1 bit)

SWIER1 : Software Interrupt on line 1
bits : 1 - 1 (1 bit)

SWIER2 : Software Interrupt on line 2
bits : 2 - 2 (1 bit)

SWIER3 : Software Interrupt on line 3
bits : 3 - 3 (1 bit)

SWIER4 : Software Interrupt on line 4
bits : 4 - 4 (1 bit)

SWIER5 : Software Interrupt on line 5
bits : 5 - 5 (1 bit)

SWIER6 : Software Interrupt on line 6
bits : 6 - 6 (1 bit)

SWIER7 : Software Interrupt on line 7
bits : 7 - 7 (1 bit)

SWIER8 : Software Interrupt on line 8
bits : 8 - 8 (1 bit)

SWIER9 : Software Interrupt on line 9
bits : 9 - 9 (1 bit)


INTFR

Pending register (EXTI_INTFR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFR INTFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF0 IF1 IF2 IF3 IF4 IF5 IF6 IF7 IF8 IF9

IF0 : Pending bit 0
bits : 0 - 0 (1 bit)

IF1 : Pending bit 1
bits : 1 - 1 (1 bit)

IF2 : Pending bit 2
bits : 2 - 2 (1 bit)

IF3 : Pending bit 3
bits : 3 - 3 (1 bit)

IF4 : Pending bit 4
bits : 4 - 4 (1 bit)

IF5 : Pending bit 5
bits : 5 - 5 (1 bit)

IF6 : Pending bit 6
bits : 6 - 6 (1 bit)

IF7 : Pending bit 7
bits : 7 - 7 (1 bit)

IF8 : Pending bit 8
bits : 8 - 8 (1 bit)

IF9 : Pending bit 9
bits : 9 - 9 (1 bit)


EVENR

Event mask register (EXTI_EVENR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENR EVENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0 MR1 MR2 MR3 MR4 MR5 MR6 MR7 MR8 MR9

MR0 : Event Mask on line 0
bits : 0 - 0 (1 bit)

MR1 : Event Mask on line 1
bits : 1 - 1 (1 bit)

MR2 : Event Mask on line 2
bits : 2 - 2 (1 bit)

MR3 : Event Mask on line 3
bits : 3 - 3 (1 bit)

MR4 : Event Mask on line 4
bits : 4 - 4 (1 bit)

MR5 : Event Mask on line 5
bits : 5 - 5 (1 bit)

MR6 : Event Mask on line 6
bits : 6 - 6 (1 bit)

MR7 : Event Mask on line 7
bits : 7 - 7 (1 bit)

MR8 : Event Mask on line 8
bits : 8 - 8 (1 bit)

MR9 : Event Mask on line 9
bits : 9 - 9 (1 bit)


RTENR

Rising Trigger selection register (EXTI_RTENR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTENR RTENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9

TR0 : Rising trigger event configuration of line 0
bits : 0 - 0 (1 bit)

TR1 : Rising trigger event configuration of line 1
bits : 1 - 1 (1 bit)

TR2 : Rising trigger event configuration of line 2
bits : 2 - 2 (1 bit)

TR3 : Rising trigger event configuration of line 3
bits : 3 - 3 (1 bit)

TR4 : Rising trigger event configuration of line 4
bits : 4 - 4 (1 bit)

TR5 : Rising trigger event configuration of line 5
bits : 5 - 5 (1 bit)

TR6 : Rising trigger event configuration of line 6
bits : 6 - 6 (1 bit)

TR7 : Rising trigger event configuration of line 7
bits : 7 - 7 (1 bit)

TR8 : Rising trigger event configuration of line 8
bits : 8 - 8 (1 bit)

TR9 : Rising trigger event configuration of line 9
bits : 9 - 9 (1 bit)


FTENR

Falling Trigger selection register (EXTI_FTENR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTENR FTENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9

TR0 : Falling trigger event configuration of line 0
bits : 0 - 0 (1 bit)

TR1 : Falling trigger event configuration of line 1
bits : 1 - 1 (1 bit)

TR2 : Falling trigger event configuration of line 2
bits : 2 - 2 (1 bit)

TR3 : Falling trigger event configuration of line 3
bits : 3 - 3 (1 bit)

TR4 : Falling trigger event configuration of line 4
bits : 4 - 4 (1 bit)

TR5 : Falling trigger event configuration of line 5
bits : 5 - 5 (1 bit)

TR6 : Falling trigger event configuration of line 6
bits : 6 - 6 (1 bit)

TR7 : Falling trigger event configuration of line 7
bits : 7 - 7 (1 bit)

TR8 : Falling trigger event configuration of line 8
bits : 8 - 8 (1 bit)

TR9 : Falling trigger event configuration of line 9
bits : 9 - 9 (1 bit)



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