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DMA1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INTFR

PADDR1

MADDR1

CFGR2

CNTR2

PADDR2

MADDR2

CFGR3

CNTR3

PADDR3

MADDR3

INTFCR

CFGR4

CNTR4

PADDR4

MADDR4

CFGR5

CNTR5

PADDR5

MADDR5

CFGR6

CNTR6

PADDR6

MADDR6

CFGR1

CFGR7

CNTR7

PADDR7

MADDR7

CNTR1


INTFR

DMA interrupt status register (DMA_INTFR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTFR INTFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIF1 TCIF1 HTIF1 TEIF1 GIF2 TCIF2 HTIF2 TEIF2 GIF3 TCIF3 HTIF3 TEIF3 GIF4 TCIF4 HTIF4 TEIF4 GIF5 TCIF5 HTIF5 TEIF5 GIF6 TCIF6 HTIF6 TEIF6 GIF7 TCIF7 HTIF7 TEIF7

GIF1 : Channel 1 Global interrupt flag
bits : 0 - 0 (1 bit)

TCIF1 : Channel 1 Transfer Complete flag
bits : 1 - 1 (1 bit)

HTIF1 : Channel 1 Half Transfer Complete flag
bits : 2 - 2 (1 bit)

TEIF1 : Channel 1 Transfer Error flag
bits : 3 - 3 (1 bit)

GIF2 : Channel 2 Global interrupt flag
bits : 4 - 4 (1 bit)

TCIF2 : Channel 2 Transfer Complete flag
bits : 5 - 5 (1 bit)

HTIF2 : Channel 2 Half Transfer Complete flag
bits : 6 - 6 (1 bit)

TEIF2 : Channel 2 Transfer Error flag
bits : 7 - 7 (1 bit)

GIF3 : Channel 3 Global interrupt flag
bits : 8 - 8 (1 bit)

TCIF3 : Channel 3 Transfer Complete flag
bits : 9 - 9 (1 bit)

HTIF3 : Channel 3 Half Transfer Complete flag
bits : 10 - 10 (1 bit)

TEIF3 : Channel 3 Transfer Error flag
bits : 11 - 11 (1 bit)

GIF4 : Channel 4 Global interrupt flag
bits : 12 - 12 (1 bit)

TCIF4 : Channel 4 Transfer Complete flag
bits : 13 - 13 (1 bit)

HTIF4 : Channel 4 Half Transfer Complete flag
bits : 14 - 14 (1 bit)

TEIF4 : Channel 4 Transfer Error flag
bits : 15 - 15 (1 bit)

GIF5 : Channel 5 Global interrupt flag
bits : 16 - 16 (1 bit)

TCIF5 : Channel 5 Transfer Complete flag
bits : 17 - 17 (1 bit)

HTIF5 : Channel 5 Half Transfer Complete flag
bits : 18 - 18 (1 bit)

TEIF5 : Channel 5 Transfer Error flag
bits : 19 - 19 (1 bit)

GIF6 : Channel 6 Global interrupt flag
bits : 20 - 20 (1 bit)

TCIF6 : Channel 6 Transfer Complete flag
bits : 21 - 21 (1 bit)

HTIF6 : Channel 6 Half Transfer Complete flag
bits : 22 - 22 (1 bit)

TEIF6 : Channel 6 Transfer Error flag
bits : 23 - 23 (1 bit)

GIF7 : Channel 7 Global interrupt flag
bits : 24 - 24 (1 bit)

TCIF7 : Channel 7 Transfer Complete flag
bits : 25 - 25 (1 bit)

HTIF7 : Channel 7 Half Transfer Complete flag
bits : 26 - 26 (1 bit)

TEIF7 : Channel 7 Transfer Error flag
bits : 27 - 27 (1 bit)


PADDR1

DMA channel 1 peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PADDR1 PADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


MADDR1

DMA channel 1 memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADDR1 MADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CFGR2

DMA channel configuration register (DMA_CFGR)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTR2

DMA channel 2 number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR2 CNTR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


PADDR2

DMA channel 2 peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PADDR2 PADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


MADDR2

DMA channel 2 memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADDR2 MADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CFGR3

DMA channel configuration register (DMA_CFGR)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR3 CFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTR3

DMA channel 3 number of data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR3 CNTR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


PADDR3

DMA channel 3 peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PADDR3 PADDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


MADDR3

DMA channel 3 memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADDR3 MADDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


INTFCR

DMA interrupt flag clear register (DMA_INTFCR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INTFCR INTFCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGIF1 CTCIF1 CHTIF1 CTEIF1 CGIF2 CTCIF2 CHTIF2 CTEIF2 CGIF3 CTCIF3 CHTIF3 CTEIF3 CGIF4 CTCIF4 CHTIF4 CTEIF4 CGIF5 CTCIF5 CHTIF5 CTEIF5 CGIF6 CTCIF6 CHTIF6 CTEIF6 CGIF7 CTCIF7 CHTIF7 CTEIF7

CGIF1 : Channel 1 Global interrupt clear
bits : 0 - 0 (1 bit)

CTCIF1 : Channel 1 Transfer Complete clear
bits : 1 - 1 (1 bit)

CHTIF1 : Channel 1 Half Transfer clear
bits : 2 - 2 (1 bit)

CTEIF1 : Channel 1 Transfer Error clear
bits : 3 - 3 (1 bit)

CGIF2 : Channel 2 Global interrupt clear
bits : 4 - 4 (1 bit)

CTCIF2 : Channel 2 Transfer Complete clear
bits : 5 - 5 (1 bit)

CHTIF2 : Channel 2 Half Transfer clear
bits : 6 - 6 (1 bit)

CTEIF2 : Channel 2 Transfer Error clear
bits : 7 - 7 (1 bit)

CGIF3 : Channel 3 Global interrupt clear
bits : 8 - 8 (1 bit)

CTCIF3 : Channel 3 Transfer Complete clear
bits : 9 - 9 (1 bit)

CHTIF3 : Channel 3 Half Transfer clear
bits : 10 - 10 (1 bit)

CTEIF3 : Channel 3 Transfer Error clear
bits : 11 - 11 (1 bit)

CGIF4 : Channel 4 Global interrupt clear
bits : 12 - 12 (1 bit)

CTCIF4 : Channel 4 Transfer Complete clear
bits : 13 - 13 (1 bit)

CHTIF4 : Channel 4 Half Transfer clear
bits : 14 - 14 (1 bit)

CTEIF4 : Channel 4 Transfer Error clear
bits : 15 - 15 (1 bit)

CGIF5 : Channel 5 Global interrupt clear
bits : 16 - 16 (1 bit)

CTCIF5 : Channel 5 Transfer Complete clear
bits : 17 - 17 (1 bit)

CHTIF5 : Channel 5 Half Transfer clear
bits : 18 - 18 (1 bit)

CTEIF5 : Channel 5 Transfer Error clear
bits : 19 - 19 (1 bit)

CGIF6 : Channel 6 Global interrupt clear
bits : 20 - 20 (1 bit)

CTCIF6 : Channel 6 Transfer Complete clear
bits : 21 - 21 (1 bit)

CHTIF6 : Channel 6 Half Transfer clear
bits : 22 - 22 (1 bit)

CTEIF6 : Channel 6 Transfer Error clear
bits : 23 - 23 (1 bit)

CGIF7 : Channel 7 Global interrupt clear
bits : 24 - 24 (1 bit)

CTCIF7 : Channel 7 Transfer Complete clear
bits : 25 - 25 (1 bit)

CHTIF7 : Channel 7 Half Transfer clear
bits : 26 - 26 (1 bit)

CTEIF7 : Channel 7 Transfer Error clear
bits : 27 - 27 (1 bit)


CFGR4

DMA channel configuration register (DMA_CFGR)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR4 CFGR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTR4

DMA channel 4 number of data register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR4 CNTR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


PADDR4

DMA channel 4 peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PADDR4 PADDR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


MADDR4

DMA channel 4 memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADDR4 MADDR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CFGR5

DMA channel configuration register (DMA_CFGR)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR5 CFGR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTR5

DMA channel 5 number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR5 CNTR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


PADDR5

DMA channel 5 peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PADDR5 PADDR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


MADDR5

DMA channel 5 memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADDR5 MADDR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CFGR6

DMA channel configuration register (DMA_CFGR)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR6 CFGR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTR6

DMA channel 6 number of data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR6 CNTR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


PADDR6

DMA channel 6 peripheral address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PADDR6 PADDR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


MADDR6

DMA channel 6 memory address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADDR6 MADDR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CFGR1

DMA channel configuration register (DMA_CFGR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CFGR7

DMA channel configuration register (DMA_CFGR)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR7 CFGR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE HTIE TEIE DIR CIRC PINC MINC PSIZE MSIZE PL MEM2MEM

EN : Channel enable
bits : 0 - 0 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)

HTIE : Half Transfer interrupt enable
bits : 2 - 2 (1 bit)

TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)

DIR : Data transfer direction
bits : 4 - 4 (1 bit)

CIRC : Circular mode
bits : 5 - 5 (1 bit)

PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)

MINC : Memory increment mode
bits : 7 - 7 (1 bit)

PSIZE : Peripheral size
bits : 8 - 9 (2 bit)

MSIZE : Memory size
bits : 10 - 11 (2 bit)

PL : Channel Priority level
bits : 12 - 13 (2 bit)

MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)


CNTR7

DMA channel 7 number of data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR7 CNTR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)


PADDR7

DMA channel 7 peripheral address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PADDR7 PADDR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA

PA : Peripheral address
bits : 0 - 31 (32 bit)


MADDR7

DMA channel 7 memory address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MADDR7 MADDR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA

MA : Memory address
bits : 0 - 31 (32 bit)


CNTR1

DMA channel 1 number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR1 CNTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDT

NDT : Number of data to transfer
bits : 0 - 15 (16 bit)



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