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TIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTLR1

INTFR

SWEVGR

CHCTLR1_Output

CHCTLR1_Input

CHCTLR2_Output

CHCTLR2_Input

CCER

CNT

PSC

ATRLR

RPTCR

CH1CVR

CH2CVR

CH3CVR

CTLR2

CH4CVR

BDTR

DMACFGR

DMAADR

SMCFGR

DMAINTENR


CTLR1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR1 CTLR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN UDIS URS OPM DIR CMS ARPE CKD CAPOV CAPLVL

CEN : Counter enable
bits : 0 - 0 (1 bit)

UDIS : Update disable
bits : 1 - 1 (1 bit)

URS : Update request source
bits : 2 - 2 (1 bit)

OPM : One-pulse mode
bits : 3 - 3 (1 bit)

DIR : Direction
bits : 4 - 4 (1 bit)

CMS : Center-aligned mode selection
bits : 5 - 6 (2 bit)

ARPE : Auto-reload preload enable
bits : 7 - 7 (1 bit)

CKD : Clock division
bits : 8 - 9 (2 bit)

CAPOV : Timer capture value configuration enable
bits : 14 - 14 (1 bit)

CAPLVL : Timer capture level indication enable
bits : 15 - 15 (1 bit)


INTFR

status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFR INTFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIF CC1IF CC2IF CC3IF CC4IF COMIF TIF BIF CC1OF CC2OF CC3OF CC4OF

UIF : Update interrupt flag
bits : 0 - 0 (1 bit)

CC1IF : Capture/compare 1 interrupt flag
bits : 1 - 1 (1 bit)

CC2IF : Capture/Compare 2 interrupt flag
bits : 2 - 2 (1 bit)

CC3IF : Capture/Compare 3 interrupt flag
bits : 3 - 3 (1 bit)

CC4IF : Capture/Compare 4 interrupt flag
bits : 4 - 4 (1 bit)

COMIF : COM interrupt flag
bits : 5 - 5 (1 bit)

TIF : Trigger interrupt flag
bits : 6 - 6 (1 bit)

BIF : Break interrupt flag
bits : 7 - 7 (1 bit)

CC1OF : Capture/Compare 1 overcapture flag
bits : 9 - 9 (1 bit)

CC2OF : Capture/compare 2 overcapture flag
bits : 10 - 10 (1 bit)

CC3OF : Capture/Compare 3 overcapture flag
bits : 11 - 11 (1 bit)

CC4OF : Capture/Compare 4 overcapture flag
bits : 12 - 12 (1 bit)


SWEVGR

event generation register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWEVGR SWEVGR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UG CC1G CC2G CC3G CC4G COMG TG BG

UG : Update generation
bits : 0 - 0 (1 bit)

CC1G : Capture/compare 1 generation
bits : 1 - 1 (1 bit)

CC2G : Capture/compare 2 generation
bits : 2 - 2 (1 bit)

CC3G : Capture/compare 3 generation
bits : 3 - 3 (1 bit)

CC4G : Capture/compare 4 generation
bits : 4 - 4 (1 bit)

COMG : Capture/Compare control update generation
bits : 5 - 5 (1 bit)

TG : Trigger generation
bits : 6 - 6 (1 bit)

BG : Break generation
bits : 7 - 7 (1 bit)


CHCTLR1_Output

capture/compare mode register (output mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTLR1_Output CHCTLR1_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S OC1FE OC1PE OC1M OC1CE CC2S OC2FE OC2PE OC2M OC2CE

CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)

OC1FE : Output Compare 1 fast enable
bits : 2 - 2 (1 bit)

OC1PE : Output Compare 1 preload enable
bits : 3 - 3 (1 bit)

OC1M : Output Compare 1 mode
bits : 4 - 6 (3 bit)

OC1CE : Output Compare 1 clear enable
bits : 7 - 7 (1 bit)

CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)

OC2FE : Output Compare 2 fast enable
bits : 10 - 10 (1 bit)

OC2PE : Output Compare 2 preload enable
bits : 11 - 11 (1 bit)

OC2M : Output Compare 2 mode
bits : 12 - 14 (3 bit)

OC2CE : Output Compare 2 clear enable
bits : 15 - 15 (1 bit)


CHCTLR1_Input

capture/compare mode register 1 (input mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTLR1_Output
reset_Mask : 0x0

CHCTLR1_Input CHCTLR1_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S IC1PSC IC1F CC2S IC2PCS IC2F

CC1S : Capture/Compare 1 selection
bits : 0 - 1 (2 bit)

IC1PSC : Input capture 1 prescaler
bits : 2 - 3 (2 bit)

IC1F : Input capture 1 filter
bits : 4 - 7 (4 bit)

CC2S : Capture/Compare 2 selection
bits : 8 - 9 (2 bit)

IC2PCS : Input capture 2 prescaler
bits : 10 - 11 (2 bit)

IC2F : Input capture 2 filter
bits : 12 - 15 (4 bit)


CHCTLR2_Output

capture/compare mode register (output mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTLR2_Output CHCTLR2_Output read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3S OC3FE OC3PE OC3M OC3CE CC4S OC4FE OC4PE OC4M OC4CE

CC3S : Capture/Compare 3 selection
bits : 0 - 1 (2 bit)

OC3FE : Output compare 3 fast enable
bits : 2 - 2 (1 bit)

OC3PE : Output compare 3 preload enable
bits : 3 - 3 (1 bit)

OC3M : Output compare 3 mode
bits : 4 - 6 (3 bit)

OC3CE : Output compare 3 clear enable
bits : 7 - 7 (1 bit)

CC4S : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)

OC4FE : Output compare 4 fast enable
bits : 10 - 10 (1 bit)

OC4PE : Output compare 4 preload enable
bits : 11 - 11 (1 bit)

OC4M : Output compare 4 mode
bits : 12 - 14 (3 bit)

OC4CE : Output compare 4 clear enable
bits : 15 - 15 (1 bit)


CHCTLR2_Input

capture/compare mode register 2 (input mode)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CHCTLR2_Output
reset_Mask : 0x0

CHCTLR2_Input CHCTLR2_Input read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3S IC3PSC IC3F CC4S IC4PSC IC4F

CC3S : Capture/compare 3 selection
bits : 0 - 1 (2 bit)

IC3PSC : Input capture 3 prescaler
bits : 2 - 3 (2 bit)

IC3F : Input capture 3 filter
bits : 4 - 7 (4 bit)

CC4S : Capture/Compare 4 selection
bits : 8 - 9 (2 bit)

IC4PSC : Input capture 4 prescaler
bits : 10 - 11 (2 bit)

IC4F : Input capture 4 filter
bits : 12 - 15 (4 bit)


CCER

capture/compare enable register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCER CCER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E CC1P CC1NE CC1NP CC2E CC2P CC2NE CC2NP CC3E CC3P CC3NE CC3NP CC4E CC4P

CC1E : Capture/Compare 1 output enable
bits : 0 - 0 (1 bit)

CC1P : Capture/Compare 1 output Polarity
bits : 1 - 1 (1 bit)

CC1NE : Capture/Compare 1 complementary output enable
bits : 2 - 2 (1 bit)

CC1NP : Capture/Compare 1 output Polarity
bits : 3 - 3 (1 bit)

CC2E : Capture/Compare 2 output enable
bits : 4 - 4 (1 bit)

CC2P : Capture/Compare 2 output Polarity
bits : 5 - 5 (1 bit)

CC2NE : Capture/Compare 2 complementary output enable
bits : 6 - 6 (1 bit)

CC2NP : Capture/Compare 2 output Polarity
bits : 7 - 7 (1 bit)

CC3E : Capture/Compare 3 output enable
bits : 8 - 8 (1 bit)

CC3P : Capture/Compare 3 output Polarity
bits : 9 - 9 (1 bit)

CC3NE : Capture/Compare 3 complementary output enable
bits : 10 - 10 (1 bit)

CC3NP : Capture/Compare 3 output Polarity
bits : 11 - 11 (1 bit)

CC4E : Capture/Compare 4 output enable
bits : 12 - 12 (1 bit)

CC4P : Capture/Compare 3 output Polarity
bits : 13 - 13 (1 bit)


CNT

counter
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : counter value
bits : 0 - 15 (16 bit)


PSC

prescaler
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC

PSC : Prescaler value
bits : 0 - 15 (16 bit)


ATRLR

auto-reload register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ATRLR ATRLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATRLR

ATRLR : Auto-reload value
bits : 0 - 15 (16 bit)


RPTCR

repetition counter register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPTCR RPTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPTCR

RPTCR : Repetition counter value
bits : 0 - 7 (8 bit)


CH1CVR

capture/compare register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CVR CH1CVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1CVR

CH1CVR : Capture/Compare 1 value
bits : 0 - 15 (16 bit)


CH2CVR

capture/compare register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CVR CH2CVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2CVR

CH2CVR : Capture/Compare 2 value
bits : 0 - 15 (16 bit)


CH3CVR

capture/compare register 3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CVR CH3CVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3CVR

CH3CVR : Capture/Compare value
bits : 0 - 15 (16 bit)


CTLR2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR2 CTLR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCPC CCUS CCDS MMS TI1S OIS1 OIS1N OIS2 OIS2N OIS3 OIS3N OIS4

CCPC : Capture/compare preloaded control
bits : 0 - 0 (1 bit)

CCUS : Capture/compare control update selection
bits : 2 - 2 (1 bit)

CCDS : Capture/compare DMA selection
bits : 3 - 3 (1 bit)

MMS : Master mode selection
bits : 4 - 6 (3 bit)

TI1S : TI1 selection
bits : 7 - 7 (1 bit)

OIS1 : Output Idle state 1
bits : 8 - 8 (1 bit)

OIS1N : Output Idle state 1
bits : 9 - 9 (1 bit)

OIS2 : Output Idle state 2
bits : 10 - 10 (1 bit)

OIS2N : Output Idle state 2
bits : 11 - 11 (1 bit)

OIS3 : Output Idle state 3
bits : 12 - 12 (1 bit)

OIS3N : Output Idle state 3
bits : 13 - 13 (1 bit)

OIS4 : Output Idle state 4
bits : 14 - 14 (1 bit)


CH4CVR

capture/compare register 4
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CVR CH4CVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH4CVR

CH4CVR : Capture/Compare value
bits : 0 - 15 (16 bit)


BDTR

break and dead-time register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTR BDTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTG LOCK OSSI OSSR BKE BKP AOE MOE

DTG : Dead-time generator setup
bits : 0 - 7 (8 bit)

LOCK : Lock configuration
bits : 8 - 9 (2 bit)

OSSI : Off-state selection for Idle mode
bits : 10 - 10 (1 bit)

OSSR : Off-state selection for Run mode
bits : 11 - 11 (1 bit)

BKE : Break enable
bits : 12 - 12 (1 bit)

BKP : Break polarity
bits : 13 - 13 (1 bit)

AOE : Automatic output enable
bits : 14 - 14 (1 bit)

MOE : Main output enable
bits : 15 - 15 (1 bit)


DMACFGR

DMA control register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACFGR DMACFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBA DBL

DBA : DMA base address
bits : 0 - 4 (5 bit)

DBL : DMA burst length
bits : 8 - 12 (5 bit)


DMAADR

DMA address for full transfer
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAADR DMAADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAB

DMAB : DMA register for burst accesses
bits : 0 - 15 (16 bit)


SMCFGR

slave mode control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

SMCFGR SMCFGR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS TS MSM ETF ETPS ECE ETP

SMS : Slave mode selection
bits : 0 - 2 (3 bit)
access : read-write

TS : Trigger selection
bits : 4 - 6 (3 bit)
access : read-write

MSM : Master/Slave mode
bits : 7 - 7 (1 bit)
access : read-write

ETF : External trigger filter
bits : 8 - 11 (4 bit)
access : read-write

ETPS : External trigger prescaler
bits : 12 - 13 (2 bit)
access : read-write

ECE : External clock enable
bits : 14 - 14 (1 bit)
access : read-write

ETP : External trigger polarity
bits : 15 - 15 (1 bit)
access : read-only


DMAINTENR

DMA/Interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAINTENR DMAINTENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UIE CC1IE CC2IE CC3IE CC4IE COMIE TIE BIE UDE CC1DE CC2DE CC3DE CC4DE COMDE TDE

UIE : Update interrupt enable
bits : 0 - 0 (1 bit)

CC1IE : Capture/Compare 1 interrupt enable
bits : 1 - 1 (1 bit)

CC2IE : Capture/Compare 2 interrupt enable
bits : 2 - 2 (1 bit)

CC3IE : Capture/Compare 3 interrupt enable
bits : 3 - 3 (1 bit)

CC4IE : Capture/Compare 4 interrupt enable
bits : 4 - 4 (1 bit)

COMIE : COM interrupt enable
bits : 5 - 5 (1 bit)

TIE : Trigger interrupt enable
bits : 6 - 6 (1 bit)

BIE : Break interrupt enable
bits : 7 - 7 (1 bit)

UDE : Update DMA request enable
bits : 8 - 8 (1 bit)

CC1DE : Capture/Compare 1 DMA request enable
bits : 9 - 9 (1 bit)

CC2DE : Capture/Compare 2 DMA request enable
bits : 10 - 10 (1 bit)

CC3DE : Capture/Compare 3 DMA request enable
bits : 11 - 11 (1 bit)

CC4DE : Capture/Compare 4 DMA request enable
bits : 12 - 12 (1 bit)

COMDE : COM DMA request enable
bits : 13 - 13 (1 bit)

TDE : Trigger DMA request enable
bits : 14 - 14 (1 bit)



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