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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

STATR

CTLR2

CTLR3

GPR

DATAR

BRR

CTLR1


STATR

Status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

STATR STATR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE FE NE ORE IDLE RXNE TC TXE LBD CTS

PE : Parity error
bits : 0 - 0 (1 bit)
access : read-only

FE : Framing error
bits : 1 - 1 (1 bit)
access : read-only

NE : Noise error flag
bits : 2 - 2 (1 bit)
access : read-only

ORE : Overrun error
bits : 3 - 3 (1 bit)
access : read-only

IDLE : IDLE line detected
bits : 4 - 4 (1 bit)
access : read-only

RXNE : Read data register not empty
bits : 5 - 5 (1 bit)
access : read-write

TC : Transmission complete
bits : 6 - 6 (1 bit)
access : read-write

TXE : Transmit data register empty
bits : 7 - 7 (1 bit)
access : read-only

LBD : LIN break detection flag
bits : 8 - 8 (1 bit)
access : read-write

CTS : CTS flag
bits : 9 - 9 (1 bit)
access : read-write


CTLR2

Control register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR2 CTLR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD LBDL LBDIE LBCL CPHA CPOL CLKEN STOP LINEN

ADD : Address of the USART node
bits : 0 - 3 (4 bit)

LBDL : lin break detection length
bits : 5 - 5 (1 bit)

LBDIE : LIN break detection interrupt enable
bits : 6 - 6 (1 bit)

LBCL : Last bit clock pulse
bits : 8 - 8 (1 bit)

CPHA : Clock phase
bits : 9 - 9 (1 bit)

CPOL : Clock polarity
bits : 10 - 10 (1 bit)

CLKEN : Clock enable
bits : 11 - 11 (1 bit)

STOP : STOP bits
bits : 12 - 13 (2 bit)

LINEN : LIN mode enable
bits : 14 - 14 (1 bit)


CTLR3

Control register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR3 CTLR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIE IREN IRLP HDSEL NACK SCEN DMAR DMAT RTSE CTSE CTSIE

EIE : Error interrupt enable
bits : 0 - 0 (1 bit)

IREN : IrDA mode enable
bits : 1 - 1 (1 bit)

IRLP : IrDA low-power
bits : 2 - 2 (1 bit)

HDSEL : Half-duplex selection
bits : 3 - 3 (1 bit)

NACK : Smartcard NACK enable
bits : 4 - 4 (1 bit)

SCEN : Smartcard mode enable
bits : 5 - 5 (1 bit)

DMAR : DMA enable receiver
bits : 6 - 6 (1 bit)

DMAT : DMA enable transmitter
bits : 7 - 7 (1 bit)

RTSE : RTS enable
bits : 8 - 8 (1 bit)

CTSE : CTS enable
bits : 9 - 9 (1 bit)

CTSIE : CTS interrupt enable
bits : 10 - 10 (1 bit)


GPR

Guard time and prescaler register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR GPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC GT

PSC : Prescaler value
bits : 0 - 7 (8 bit)

GT : Guard time value
bits : 8 - 15 (8 bit)


DATAR

Data register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAR DATAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DR

DR : Data value
bits : 0 - 8 (9 bit)


BRR

Baud rate register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRR BRR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_Fraction DIV_Mantissa

DIV_Fraction : fraction of USARTDIV
bits : 0 - 3 (4 bit)

DIV_Mantissa : mantissa of USARTDIV
bits : 4 - 15 (12 bit)


CTLR1

Control register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR1 CTLR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBK RWU RE TE IDLEIE RXNEIE TCIE TXEIE PEIE PS PCE WAKE M UE

SBK : Send break
bits : 0 - 0 (1 bit)

RWU : Receiver wakeup
bits : 1 - 1 (1 bit)

RE : Receiver enable
bits : 2 - 2 (1 bit)

TE : Transmitter enable
bits : 3 - 3 (1 bit)

IDLEIE : IDLE interrupt enable
bits : 4 - 4 (1 bit)

RXNEIE : RXNE interrupt enable
bits : 5 - 5 (1 bit)

TCIE : Transmission complete interrupt enable
bits : 6 - 6 (1 bit)

TXEIE : TXE interrupt enable
bits : 7 - 7 (1 bit)

PEIE : PE interrupt enable
bits : 8 - 8 (1 bit)

PS : Parity selection
bits : 9 - 9 (1 bit)

PCE : Parity control enable
bits : 10 - 10 (1 bit)

WAKE : Wakeup method
bits : 11 - 11 (1 bit)

M : Word length
bits : 12 - 12 (1 bit)

UE : USART enable
bits : 13 - 13 (1 bit)



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