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ADC1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

STATR

SAMPTR2_CHARGE2 (SAMPTR2)

IOFR1

IOFR2

IOFR3

IOFR4

WDHTR

WDLTR

RSQR1

RSQR2

RSQR3

ISQR

IDATAR1

CTLR1

IDATAR2

IDATAR3

IDATAR4

RDATAR

DLYR

CTLR2

SAMPTR1_CHARGE1 (SAMPTR1)


STATR

status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATR STATR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD EOC JEOC JSTRT STRT

AWD : Analog watchdog flag
bits : 0 - 0 (1 bit)

EOC : Regular channel end of conversion
bits : 1 - 1 (1 bit)

JEOC : Injected channel end of conversion
bits : 2 - 2 (1 bit)

JSTRT : Injected channel start flag
bits : 3 - 3 (1 bit)

STRT : Regular channel start flag
bits : 4 - 4 (1 bit)


SAMPTR2_CHARGE2 (SAMPTR2)

sample time register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPTR2_CHARGE2 SAMPTR2_CHARGE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP0 SMP1 SMP2 SMP3 SMP4 SMP5 SMP6_TKCG6 SMP7 SMP8 SMP9

SMP0 : Channel 0 sample time selection
bits : 0 - 2 (3 bit)

SMP1 : Channel 1 sample time selection
bits : 3 - 5 (3 bit)

SMP2 : Channel 2 sample time selection
bits : 6 - 8 (3 bit)

SMP3 : Channel 3 sample time selection
bits : 9 - 11 (3 bit)

SMP4 : Channel 4 sample time selection
bits : 12 - 14 (3 bit)

SMP5 : Channel 5 sample time selection
bits : 15 - 17 (3 bit)

SMP6_TKCG6 : Channel 6 sample time selection
bits : 18 - 20 (3 bit)

SMP7 : Channel 7 sample time selection
bits : 21 - 23 (3 bit)

SMP8 : Channel 8 sample time selection
bits : 24 - 26 (3 bit)

SMP9 : Channel 9 sample time selection
bits : 27 - 29 (3 bit)


IOFR1

injected channel data offset register x
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFR1 IOFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET1

JOFFSET1 : Data offset for injected channel x
bits : 0 - 9 (10 bit)


IOFR2

injected channel data offset register x
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFR2 IOFR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET2

JOFFSET2 : Data offset for injected channel x
bits : 0 - 9 (10 bit)


IOFR3

injected channel data offset register x
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFR3 IOFR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET3

JOFFSET3 : Data offset for injected channel x
bits : 0 - 9 (10 bit)


IOFR4

injected channel data offset register x
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFR4 IOFR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET4

JOFFSET4 : Data offset for injected channel x
bits : 0 - 9 (10 bit)


WDHTR

watchdog higher threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDHTR WDHTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HT

HT : Analog watchdog higher threshold
bits : 0 - 9 (10 bit)


WDLTR

watchdog lower threshold register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDLTR WDLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LT

LT : Analog watchdog lower threshold
bits : 0 - 9 (10 bit)


RSQR1

regular sequence register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQR1 RSQR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ13 SQ14 SQ15 SQ16 L

SQ13 : 13th conversion in regular sequence
bits : 0 - 4 (5 bit)

SQ14 : 14th conversion in regular sequence
bits : 5 - 9 (5 bit)

SQ15 : 15th conversion in regular sequence
bits : 10 - 14 (5 bit)

SQ16 : 16th conversion in regular sequence
bits : 15 - 19 (5 bit)

L : Regular channel sequence length
bits : 20 - 23 (4 bit)


RSQR2

regular sequence register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQR2 RSQR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ7 SQ8 SQ9 SQ10 SQ11 SQ12

SQ7 : 7th conversion in regular sequence
bits : 0 - 4 (5 bit)

SQ8 : 8th conversion in regular sequence
bits : 5 - 9 (5 bit)

SQ9 : 9th conversion in regular sequence
bits : 10 - 14 (5 bit)

SQ10 : 10th conversion in regular sequence
bits : 15 - 19 (5 bit)

SQ11 : 11th conversion in regular sequence
bits : 20 - 24 (5 bit)

SQ12 : 12th conversion in regular sequence
bits : 25 - 29 (5 bit)


RSQR3

regular sequence register 3
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQR3 RSQR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ1 SQ2 SQ3 SQ4 SQ5 SQ6

SQ1 : 1st conversion in regular sequence
bits : 0 - 4 (5 bit)

SQ2 : 2nd conversion in regular sequence
bits : 5 - 9 (5 bit)

SQ3 : 3rd conversion in regular sequence
bits : 10 - 14 (5 bit)

SQ4 : 4th conversion in regular sequence
bits : 15 - 19 (5 bit)

SQ5 : 5th conversion in regular sequence
bits : 20 - 24 (5 bit)

SQ6 : 6th conversion in regular sequence
bits : 25 - 29 (5 bit)


ISQR

injected sequence register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISQR ISQR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JSQ1 JSQ2 JSQ3 JSQ4 JL

JSQ1 : 1st conversion in injected sequence
bits : 0 - 4 (5 bit)

JSQ2 : 2nd conversion in injected sequence
bits : 5 - 9 (5 bit)

JSQ3 : 3rd conversion in injected sequence
bits : 10 - 14 (5 bit)

JSQ4 : 4th conversion in injected sequence
bits : 15 - 19 (5 bit)

JL : Injected sequence length
bits : 20 - 21 (2 bit)


IDATAR1

injected data register 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR1 IDATAR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Injected data
bits : 0 - 15 (16 bit)


CTLR1

control register 1/TKEY_V_CTLR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR1 CTLR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWDCH EOCIE AWDIE JEOCIE SCAN AWDSGL JAUTO DISCEN JDISCEN DISCNUM JAWDEN AWDEN CALVOL

AWDCH : Analog watchdog channel select bits
bits : 0 - 4 (5 bit)

EOCIE : Interrupt enable for EOC
bits : 5 - 5 (1 bit)

AWDIE : Analog watchdog interrupt enable
bits : 6 - 6 (1 bit)

JEOCIE : Interrupt enable for injected channels
bits : 7 - 7 (1 bit)

SCAN : Scan mode enable
bits : 8 - 8 (1 bit)

AWDSGL : Enable the watchdog on a single channel in scan mode
bits : 9 - 9 (1 bit)

JAUTO : Automatic injected group conversion
bits : 10 - 10 (1 bit)

DISCEN : Discontinuous mode on regular channels
bits : 11 - 11 (1 bit)

JDISCEN : Discontinuous mode on injected channels
bits : 12 - 12 (1 bit)

DISCNUM : Discontinuous mode channel count
bits : 13 - 15 (3 bit)

JAWDEN : Analog watchdog enable on injected channels
bits : 22 - 22 (1 bit)

AWDEN : Analog watchdog enable on regular channels
bits : 23 - 23 (1 bit)

CALVOL : ADC Calibration voltage selection
bits : 25 - 26 (2 bit)


IDATAR2

injected data register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR2 IDATAR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Injected data
bits : 0 - 15 (16 bit)


IDATAR3

injected data register 3
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR3 IDATAR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Injected data
bits : 0 - 15 (16 bit)


IDATAR4

injected data register 4
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR4 IDATAR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Injected data
bits : 0 - 15 (16 bit)


RDATAR

regular data register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDATAR RDATAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Regular data
bits : 0 - 31 (32 bit)


DLYR

delay data register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLYR DLYR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLYVLU DLYSRC

DLYVLU : External trigger data delay time configuration
bits : 0 - 8 (9 bit)

DLYSRC : External trigger source delay selection
bits : 9 - 9 (1 bit)


CTLR2

control register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR2 CTLR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADON CONT CAL RSTCAL DMA ALIGN JEXTSEL JEXTTRIG EXTSEL EXTTRIG JSWSTART SWSTART

ADON : A/D converter ON / OFF
bits : 0 - 0 (1 bit)

CONT : Continuous conversion
bits : 1 - 1 (1 bit)

CAL : A/D calibration
bits : 2 - 2 (1 bit)

RSTCAL : Reset calibration
bits : 3 - 3 (1 bit)

DMA : Direct memory access mode
bits : 8 - 8 (1 bit)

ALIGN : Data alignment
bits : 11 - 11 (1 bit)

JEXTSEL : External event select for injected group
bits : 12 - 14 (3 bit)

JEXTTRIG : External trigger conversion mode for injected channels
bits : 15 - 15 (1 bit)

EXTSEL : External event select for regular group
bits : 17 - 19 (3 bit)

EXTTRIG : External trigger conversion mode for regular channels
bits : 20 - 20 (1 bit)

JSWSTART : Start conversion of injected channels
bits : 21 - 21 (1 bit)

SWSTART : Start conversion of regular channels
bits : 22 - 22 (1 bit)


SAMPTR1_CHARGE1 (SAMPTR1)

sample time register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPTR1_CHARGE1 SAMPTR1_CHARGE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMP10 SMP11 SMP12_TKCG12 SMP13 SMP14 SMP15

SMP10 : Channel 10 sample time selection
bits : 0 - 2 (3 bit)

SMP11 : Channel 11 sample time selection
bits : 3 - 5 (3 bit)

SMP12_TKCG12 : Channel 12 sample time selection
bits : 6 - 8 (3 bit)

SMP13 : Channel 13 sample time selection
bits : 9 - 11 (3 bit)

SMP14 : Channel 14 sample time selection
bits : 12 - 14 (3 bit)

SMP15 : Channel 15 sample time selection
bits : 15 - 17 (3 bit)



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