\n

DBG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR


CR

DBGMCU_CFGR1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEP STOP STANDBY IWDG_STOP WWDG_STOP TIM1_STOP TIM2_STOP

SLEEP : Debug Sleep mode
bits : 0 - 0 (1 bit)

STOP : Debug stop mode
bits : 1 - 1 (1 bit)

STANDBY : Debug standby mode
bits : 2 - 2 (1 bit)

IWDG_STOP : IWDG_STOP
bits : 8 - 8 (1 bit)

WWDG_STOP : WWDG_STOP
bits : 9 - 9 (1 bit)

TIM1_STOP : TIM1_STOP
bits : 12 - 12 (1 bit)

TIM2_STOP : TIM2_STOP
bits : 13 - 13 (1 bit)



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