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FLASH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ACTLR

CTLR

ADDR

OBR

WPR

MODEKEYR

BOOT_MODEKEYP

KEYR

OBKEYR

STATR


ACTLR

Flash key register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

ACTLR ACTLR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY

LATENCY : Number of FLASH wait states
bits : 0 - 1 (2 bit)
access : read-write


CTLR

Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER OBPG OBER STRT LOCK OBWRE ERRIE EOPIE FLOCK FTPG FTER BUFLOAD BUFRST

PG : Programming
bits : 0 - 0 (1 bit)

PER : Page Erase
bits : 1 - 1 (1 bit)

MER : Mass Erase
bits : 2 - 2 (1 bit)

OBPG : Option byte programming
bits : 4 - 4 (1 bit)

OBER : Option byte erase
bits : 5 - 5 (1 bit)

STRT : Start
bits : 6 - 6 (1 bit)

LOCK : Lock
bits : 7 - 7 (1 bit)

OBWRE : Option bytes write enable
bits : 9 - 9 (1 bit)

ERRIE : Error interrupt enable
bits : 10 - 10 (1 bit)

EOPIE : End of operation interrupt enable
bits : 12 - 12 (1 bit)

FLOCK : Fast programmable lock
bits : 15 - 15 (1 bit)

FTPG : Fast programming
bits : 16 - 16 (1 bit)

FTER : Fast erase
bits : 17 - 17 (1 bit)

BUFLOAD : Buffer load
bits : 18 - 18 (1 bit)

BUFRST : Buffer reset
bits : 19 - 19 (1 bit)


ADDR

Flash address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAR

FAR : Flash Address
bits : 0 - 31 (32 bit)


OBR

Option byte register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OBR OBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OBERR RDPRT IWDG_SW STANDY_RST RST_MODE STATR_MODE DATA0 DATA1

OBERR : Option byte error
bits : 0 - 0 (1 bit)

RDPRT : Read protection
bits : 1 - 1 (1 bit)

IWDG_SW : IWDG_SW
bits : 2 - 2 (1 bit)

STANDY_RST : STANDY_RST
bits : 4 - 4 (1 bit)

RST_MODE : CFG_RST_MODE
bits : 5 - 6 (2 bit)

STATR_MODE : STATR MODE
bits : 7 - 7 (1 bit)

DATA0 : DATA0
bits : 10 - 17 (8 bit)

DATA1 : DATA1
bits : 18 - 25 (8 bit)


WPR

Write protection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPR WPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP

WRP : Write protect
bits : 0 - 15 (16 bit)


MODEKEYR

Mode select register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MODEKEYR MODEKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEKEYR

MODEKEYR : Mode select
bits : 0 - 31 (32 bit)


BOOT_MODEKEYP

Boot mode key register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BOOT_MODEKEYP BOOT_MODEKEYP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEKEYR

MODEKEYR : Boot mode key
bits : 0 - 31 (32 bit)


KEYR

Flash key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYR KEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYR

KEYR : FPEC key
bits : 0 - 31 (32 bit)


OBKEYR

Flash option key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OBKEYR OBKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTKEY

OPTKEY : Option byte key
bits : 0 - 31 (32 bit)


STATR

Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

STATR STATR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSY WRPRTERR EOP BOOT_MODE BOOT_LOCK

BSY : Busy
bits : 0 - 0 (1 bit)
access : read-only

WRPRTERR : Write protection error
bits : 4 - 4 (1 bit)
access : read-write

EOP : End of operation
bits : 5 - 5 (1 bit)
access : read-write

BOOT_MODE : BOOT mode
bits : 14 - 14 (1 bit)
access : read-write

BOOT_LOCK : BOOT lock
bits : 15 - 15 (1 bit)
access : read-write



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