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PFIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISR1

IENR1

STK_CTLR

STK_SR

STK_CNTL

STK_CMPLR

IENR2

IRER1

IRER2

IPR1

IPSR1

IPSR2

IPR2

IPRR1

IPRR2

IACTR1

IACTR2

ISR2

ITHRESDR

IPRIOR0

IPRIOR1

IPRIOR2

IPRIOR3

IPRIOR4

IPRIOR5

IPRIOR6

IPRIOR7

IPRIOR8

IPRIOR9

IPRIOR10

IPRIOR11

IPRIOR12

IPRIOR13

IPRIOR14

IPRIOR15

IPRIOR6 (IPRIOR16)

IPRIOR7 (IPRIOR17)

IPRIOR8 (IPRIOR18)

IPRIOR9 (IPRIOR19)

IPRIOR20

IPRIOR21

IPRIOR22

IPRIOR23

IPRIOR24

IPRIOR25

IPRIOR26

IPRIOR27

IPRIOR28

IPRIOR29

IPRIOR30

IPRIOR31

IPRIOR32

IPRIOR33

IPRIOR34

IPRIOR35

IPRIOR36

IPRIOR37

IPRIOR38

IPRIOR39

IPRIOR40

IPRIOR41

IPRIOR42

IPRIOR43

IPRIOR44

IPRIOR45

IPRIOR46

IPRIOR47

IPRIOR48

IPRIOR49

IPRIOR50

IPRIOR51

IPRIOR52

IPRIOR53

IPRIOR54

IPRIOR55

IPRIOR56

IPRIOR57

IPRIOR58

IPRIOR59

IPRIOR60

IPRIOR61

IPRIOR62

IPRIOR63

CFGR

GISR

VTFIDR

VTFADDRR0

VTFADDRR1

SCTLR


ISR1

Interrupt Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR1 ISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTENSTA2_3 INTENSTA12 INTENSTA14 INTENSTA16_31

INTENSTA2_3 : Interrupt ID Status
bits : 2 - 3 (2 bit)

INTENSTA12 : Interrupt ID Status
bits : 12 - 12 (1 bit)

INTENSTA14 : Interrupt ID Status
bits : 14 - 14 (1 bit)

INTENSTA16_31 : Interrupt ID Status
bits : 16 - 31 (16 bit)


IENR1

Interrupt Setting Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IENR1 IENR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTEN12 INTEN14 INTEN16_31

INTEN12 : INTEN12
bits : 12 - 12 (1 bit)

INTEN14 : INTEN14
bits : 14 - 14 (1 bit)

INTEN16_31 : INTEN16_31
bits : 16 - 31 (16 bit)


STK_CTLR

System counter control register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

STK_CTLR STK_CTLR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STE STIE STCLK STRE MODE INIT SWIE

STE : System counter enable
bits : 0 - 0 (1 bit)
access : read-write

STIE : System counter interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

STCLK : System selects the clock source
bits : 2 - 2 (1 bit)
access : read-write

STRE : System reload register
bits : 3 - 3 (1 bit)
access : read-write

MODE : System Mode
bits : 4 - 4 (1 bit)
access : read-write

INIT : System Initialization update
bits : 5 - 5 (1 bit)
access : read-write

SWIE : System software triggered interrupts enable
bits : 31 - 31 (1 bit)
access : read-write


STK_SR

System START
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STK_SR STK_SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTIF

CNTIF : CNTIF
bits : 0 - 0 (1 bit)


STK_CNTL

System counter low register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STK_CNTL STK_CNTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : CNT
bits : 0 - 31 (32 bit)


STK_CMPLR

System compare low register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STK_CMPLR STK_CMPLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : CMP
bits : 0 - 31 (32 bit)


IENR2

Interrupt Setting Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IENR2 IENR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTEN

INTEN : INTEN32_38
bits : 0 - 6 (7 bit)


IRER1

Interrupt Clear Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IRER1 IRER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRSET12 INTRSET14 INTRSET16_31

INTRSET12 : INTRSET12
bits : 12 - 12 (1 bit)

INTRSET14 : INTRSET14
bits : 14 - 14 (1 bit)

INTRSET16_31 : INTRSET16_31
bits : 16 - 31 (16 bit)


IRER2

Interrupt Clear Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IRER2 IRER2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTRSET38_32

INTRSET38_32 : INTRSET38_32
bits : 0 - 6 (7 bit)


IPR1

Interrupt Pending Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPR1 IPR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDSTA2_3 PENDSTA12 INTENSTA14 INTENSTA16_31

PENDSTA2_3 : PENDSTA
bits : 2 - 3 (2 bit)

PENDSTA12 : PENDSTA
bits : 12 - 12 (1 bit)

INTENSTA14 : PENDSTA
bits : 14 - 14 (1 bit)

INTENSTA16_31 : PENDSTA
bits : 16 - 31 (16 bit)


IPSR1

Interrupt Pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IPSR1 IPSR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDSET2_3 PENDSET12 PENDSET14 PENDSET16_31

PENDSET2_3 : PENDSET
bits : 2 - 3 (2 bit)

PENDSET12 : PENDSET
bits : 12 - 12 (1 bit)

PENDSET14 : PENDSET
bits : 14 - 14 (1 bit)

PENDSET16_31 : PENDSET
bits : 16 - 31 (16 bit)


IPSR2

Interrupt Pending Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IPSR2 IPSR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDSET32_38

PENDSET32_38 : PENDSET32_38
bits : 0 - 6 (7 bit)


IPR2

Interrupt Pending Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPR2 IPR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDSTA32_38

PENDSTA32_38 : PENDSTA
bits : 0 - 6 (7 bit)


IPRR1

Interrupt Pending Clear Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IPRR1 IPRR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDRST2_3 PENDRST12 PENDRST14 PENDRST16_31

PENDRST2_3 : PENDRESET
bits : 2 - 3 (2 bit)

PENDRST12 : PENDRESET
bits : 12 - 12 (1 bit)

PENDRST14 : PENDRESET
bits : 14 - 14 (1 bit)

PENDRST16_31 : PENDRESET
bits : 16 - 31 (16 bit)


IPRR2

Interrupt Pending Clear Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IPRR2 IPRR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDRST32_38

PENDRST32_38 : PENDRESET32_38
bits : 0 - 6 (7 bit)


IACTR1

Interrupt ACTIVE Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IACTR1 IACTR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IACTS2_3 IACTS12 IACTS14 IACTS16_31

IACTS2_3 : IACTS
bits : 2 - 3 (2 bit)

IACTS12 : IACTS
bits : 12 - 12 (1 bit)

IACTS14 : IACTS
bits : 14 - 14 (1 bit)

IACTS16_31 : IACTS
bits : 16 - 31 (16 bit)


IACTR2

Interrupt ACTIVE Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IACTR2 IACTR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IACTS

IACTS : IACTS
bits : 0 - 6 (7 bit)


ISR2

Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR2 ISR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTENSTA

INTENSTA : Interrupt ID Status
bits : 0 - 6 (7 bit)


ITHRESDR

Interrupt Priority Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITHRESDR ITHRESDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THRESHOLD

THRESHOLD : THRESHOLD
bits : 0 - 7 (8 bit)


IPRIOR0

Interrupt Priority Register
address_offset : 0x400 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR0 IPRIOR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR1

Interrupt Priority Register
address_offset : 0x401 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR1 IPRIOR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR2

Interrupt Priority Register
address_offset : 0x402 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR2 IPRIOR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR3

Interrupt Priority Register
address_offset : 0x403 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR3 IPRIOR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR4

Interrupt Priority Register
address_offset : 0x404 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR4 IPRIOR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR5

Interrupt Priority Register
address_offset : 0x405 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR5 IPRIOR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR6

Interrupt Priority Register
address_offset : 0x406 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR6 IPRIOR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR7

Interrupt Priority Register
address_offset : 0x407 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR7 IPRIOR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR8

Interrupt Priority Register
address_offset : 0x408 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR8 IPRIOR8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR9

Interrupt Priority Register
address_offset : 0x409 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR9 IPRIOR9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR10

Interrupt Priority Register
address_offset : 0x40A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR10 IPRIOR10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR11

Interrupt Priority Register
address_offset : 0x40B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR11 IPRIOR11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR12

Interrupt Priority Register
address_offset : 0x40C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR12 IPRIOR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR13

Interrupt Priority Register
address_offset : 0x40D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR13 IPRIOR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR14

Interrupt Priority Register
address_offset : 0x40E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR14 IPRIOR14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR15

Interrupt Priority Register
address_offset : 0x40F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR15 IPRIOR15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR6 (IPRIOR16)

Interrupt Priority Register
address_offset : 0x410 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR6 IPRIOR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR7 (IPRIOR17)

Interrupt Priority Register
address_offset : 0x411 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR7 IPRIOR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR8 (IPRIOR18)

Interrupt Priority Register
address_offset : 0x412 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR8 IPRIOR8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR9 (IPRIOR19)

Interrupt Priority Register
address_offset : 0x413 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR9 IPRIOR9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR20

Interrupt Priority Register
address_offset : 0x414 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR20 IPRIOR20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR21

Interrupt Priority Register
address_offset : 0x415 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR21 IPRIOR21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR22

Interrupt Priority Register
address_offset : 0x416 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR22 IPRIOR22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR23

Interrupt Priority Register
address_offset : 0x417 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR23 IPRIOR23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR24

Interrupt Priority Register
address_offset : 0x418 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR24 IPRIOR24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR25

Interrupt Priority Register
address_offset : 0x419 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR25 IPRIOR25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR26

Interrupt Priority Register
address_offset : 0x41A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR26 IPRIOR26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR27

Interrupt Priority Register
address_offset : 0x41B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR27 IPRIOR27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR28

Interrupt Priority Register
address_offset : 0x41C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR28 IPRIOR28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR29

Interrupt Priority Register
address_offset : 0x41D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR29 IPRIOR29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR30

Interrupt Priority Register
address_offset : 0x41E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR30 IPRIOR30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR31

Interrupt Priority Register
address_offset : 0x41F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR31 IPRIOR31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR32

Interrupt Priority Register
address_offset : 0x420 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR32 IPRIOR32 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR33

Interrupt Priority Register
address_offset : 0x421 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR33 IPRIOR33 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR34

Interrupt Priority Register
address_offset : 0x422 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR34 IPRIOR34 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR35

Interrupt Priority Register
address_offset : 0x423 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR35 IPRIOR35 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR36

Interrupt Priority Register
address_offset : 0x424 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR36 IPRIOR36 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR37

Interrupt Priority Register
address_offset : 0x425 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR37 IPRIOR37 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR38

Interrupt Priority Register
address_offset : 0x426 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR38 IPRIOR38 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR39

Interrupt Priority Register
address_offset : 0x427 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR39 IPRIOR39 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR40

Interrupt Priority Register
address_offset : 0x428 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR40 IPRIOR40 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR41

Interrupt Priority Register
address_offset : 0x429 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR41 IPRIOR41 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR42

Interrupt Priority Register
address_offset : 0x42A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR42 IPRIOR42 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR43

Interrupt Priority Register
address_offset : 0x42B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR43 IPRIOR43 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR44

Interrupt Priority Register
address_offset : 0x42C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR44 IPRIOR44 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR45

Interrupt Priority Register
address_offset : 0x42D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR45 IPRIOR45 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR46

Interrupt Priority Register
address_offset : 0x42E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR46 IPRIOR46 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR47

Interrupt Priority Register
address_offset : 0x42F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR47 IPRIOR47 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR48

Interrupt Priority Register
address_offset : 0x430 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR48 IPRIOR48 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR49

Interrupt Priority Register
address_offset : 0x431 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR49 IPRIOR49 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR50

Interrupt Priority Register
address_offset : 0x432 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR50 IPRIOR50 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR51

Interrupt Priority Register
address_offset : 0x433 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR51 IPRIOR51 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR52

Interrupt Priority Register
address_offset : 0x434 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR52 IPRIOR52 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR53

Interrupt Priority Register
address_offset : 0x435 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR53 IPRIOR53 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR54

Interrupt Priority Register
address_offset : 0x436 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR54 IPRIOR54 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR55

Interrupt Priority Register
address_offset : 0x437 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR55 IPRIOR55 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR56

Interrupt Priority Register
address_offset : 0x438 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR56 IPRIOR56 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR57

Interrupt Priority Register
address_offset : 0x439 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR57 IPRIOR57 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR58

Interrupt Priority Register
address_offset : 0x43A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR58 IPRIOR58 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR59

Interrupt Priority Register
address_offset : 0x43B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR59 IPRIOR59 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR60

Interrupt Priority Register
address_offset : 0x43C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR60 IPRIOR60 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR61

Interrupt Priority Register
address_offset : 0x43D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR61 IPRIOR61 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR62

Interrupt Priority Register
address_offset : 0x43E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR62 IPRIOR62 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

IPRIOR63

Interrupt Priority Register
address_offset : 0x43F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRIOR63 IPRIOR63 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CFGR

Interrupt Config Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTSYS KEYCODE

RSTSYS : RESET System
bits : 7 - 7 (1 bit)
access : write-only

KEYCODE : KEYCODE
bits : 16 - 31 (16 bit)
access : write-only


GISR

Interrupt Global Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GISR GISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NESTSTA GACTSTA GPENDSTA

NESTSTA : NESTSTA
bits : 0 - 7 (8 bit)

GACTSTA : GACTSTA
bits : 8 - 8 (1 bit)

GPENDSTA : GPENDSTA
bits : 9 - 9 (1 bit)


VTFIDR

ID Config Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTFIDR VTFIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTFID0 VTFID1

VTFID0 : VTFID0
bits : 0 - 7 (8 bit)

VTFID1 : VTFID1
bits : 8 - 15 (8 bit)


VTFADDRR0

Interrupt 0 address Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTFADDRR0 VTFADDRR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTF0EN ADDR0

VTF0EN : VTF0EN
bits : 0 - 0 (1 bit)

ADDR0 : ADDR0
bits : 1 - 31 (31 bit)


VTFADDRR1

Interrupt 1 address Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTFADDRR1 VTFADDRR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTF1EN ADDR1

VTF1EN : VTF1EN
bits : 0 - 0 (1 bit)

ADDR1 : ADDR1
bits : 1 - 31 (31 bit)


SCTLR

System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTLR SCTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEPONEXIT SLEEPDEEP WFITOWFE SEVONPEND SETEVENT SYSRST

SLEEPONEXIT : SLEEPONEXIT
bits : 1 - 1 (1 bit)

SLEEPDEEP : SLEEPDEEP
bits : 2 - 2 (1 bit)

WFITOWFE : WFITOWFE
bits : 3 - 3 (1 bit)

SEVONPEND : SEVONPEND
bits : 4 - 4 (1 bit)

SETEVENT : SETEVENT
bits : 5 - 5 (1 bit)

SYSRST : SYSRESET
bits : 31 - 31 (1 bit)



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