\n

RNG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

SR

DR


CR

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RNGEN IE

RNGEN : Random number generator enable
bits : 2 - 2 (1 bit)

IE : Interrupt enable
bits : 3 - 3 (1 bit)


SR

status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

SR SR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDY CECS SECS CEIS SEIS

DRDY : Data ready
bits : 0 - 0 (1 bit)
access : read-only

CECS : Clock error current status
bits : 1 - 1 (1 bit)
access : read-only

SECS : Seed error current status
bits : 2 - 2 (1 bit)
access : read-only

CEIS : Clock error interrupt status
bits : 5 - 5 (1 bit)
access : read-write

SEIS : Seed error interrupt status
bits : 6 - 6 (1 bit)
access : read-write


DR

data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RNDATA

RNDATA : Random data
bits : 0 - 31 (32 bit)



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