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ETHERNET

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

MACCR

MACMIIAR

MACMIIDR

MACFCR

MACVLANTR

MACRWUFFR

MACPMTCSR

MACSR

MACIMR

MACFFR

MACA0HR

MACA0LR

MACA1HR

MACA1LR

MACA2HR

MACA2LR

MACA3HR

MACA3LR

MACHTHR

MACHTLR


MACCR

Ethernet MAC configuration register (ETH_MACCR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACCR MACCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCES TCF RE TE DC BL APCS RD IPCO DM LM ROD FES CSD IFG IRE PDI JD WD TCD

TCES : Send clock selection bit
bits : 0 - 0 (1 bit)

TCF : Send clock reversal
bits : 1 - 1 (1 bit)

RE : Receiver enable
bits : 2 - 2 (1 bit)

TE : Transmitter enable
bits : 3 - 3 (1 bit)

DC : Deferral check
bits : 4 - 4 (1 bit)

BL : Back-off limit
bits : 5 - 6 (2 bit)

APCS : Automatic pad/CRC stripping
bits : 7 - 7 (1 bit)

RD : Retry disable
bits : 9 - 9 (1 bit)

IPCO : IPv4 checksum offload
bits : 10 - 10 (1 bit)

DM : Duplex mode
bits : 11 - 11 (1 bit)

LM : Loopback mode
bits : 12 - 12 (1 bit)

ROD : Receive own disable
bits : 13 - 13 (1 bit)

FES : Fast Ethernet speed
bits : 14 - 14 (1 bit)

CSD : Carrier sense disable
bits : 16 - 16 (1 bit)

IFG : Interframe gap
bits : 17 - 19 (3 bit)

IRE : 10MPHY 50Ω set
bits : 20 - 20 (1 bit)

PDI : 10MPHY TX DRIVER bisa current
bits : 21 - 21 (1 bit)

JD : Jabber disable
bits : 22 - 22 (1 bit)

WD : Watchdog disable
bits : 23 - 23 (1 bit)

TCD : SEND clock delay
bits : 29 - 31 (3 bit)


MACMIIAR

Ethernet MAC MII address register (ETH_MACMIIAR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMIIAR MACMIIAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MB MW CR MR PA

MB : MII busy
bits : 0 - 0 (1 bit)

MW : MII write
bits : 1 - 1 (1 bit)

CR : Clock range
bits : 2 - 4 (3 bit)

MR : MII register
bits : 6 - 10 (5 bit)

PA : PHY address
bits : 11 - 15 (5 bit)


MACMIIDR

Ethernet MAC MII data register (ETH_MACMIIDR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMIIDR MACMIIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD

MD : MII data
bits : 0 - 15 (16 bit)


MACFCR

Ethernet MAC flow control register (ETH_MACFCR)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACFCR MACFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCB_BPA TFCE RFCE UPFD PLT ZQPD PT

FCB_BPA : Flow control busy/back pressure activate
bits : 0 - 0 (1 bit)

TFCE : Transmit flow control enable
bits : 1 - 1 (1 bit)

RFCE : Receive flow control enable
bits : 2 - 2 (1 bit)

UPFD : Unicast pause frame detect
bits : 3 - 3 (1 bit)

PLT : Pause low threshold
bits : 4 - 5 (2 bit)

ZQPD : Zero-quanta pause disable
bits : 7 - 7 (1 bit)

PT : Pass control frames
bits : 16 - 31 (16 bit)


MACVLANTR

Ethernet MAC VLAN tag register (ETH_MACVLANTR)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACVLANTR MACVLANTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLANTI VLANTC

VLANTI : VLAN tag identifier (for receive frames)
bits : 0 - 15 (16 bit)

VLANTC : 12-bit VLAN tag comparison
bits : 16 - 16 (1 bit)


MACRWUFFR

Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRWUFFR MACRWUFFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MACPMTCSR

Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPMTCSR MACPMTCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD MPE WFE MPR WFR GU WFFRPR

PD : Power down
bits : 0 - 0 (1 bit)

MPE : Magic Packet enable
bits : 1 - 1 (1 bit)

WFE : Wakeup frame enable
bits : 2 - 2 (1 bit)

MPR : Magic packet received
bits : 5 - 5 (1 bit)

WFR : Wakeup frame received
bits : 6 - 6 (1 bit)

GU : Global unicast
bits : 9 - 9 (1 bit)

WFFRPR : Wakeup frame filter register pointer reset
bits : 31 - 31 (1 bit)


MACSR

Ethernet MAC interrupt status register (ETH_MACSR)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSR MACSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMTS MMCS MMCRS MMCTS TSTS

PMTS : PMT status
bits : 3 - 3 (1 bit)

MMCS : MMC status
bits : 4 - 4 (1 bit)

MMCRS : MMC receive status
bits : 5 - 5 (1 bit)

MMCTS : MMC transmit status
bits : 6 - 6 (1 bit)

TSTS : Time stamp trigger status
bits : 9 - 9 (1 bit)


MACIMR

Ethernet MAC interrupt mask register (ETH_MACIMR)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACIMR MACIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMTIM TSTIM

PMTIM : PMT interrupt mask
bits : 3 - 3 (1 bit)

TSTIM : Time stamp trigger interrupt mask
bits : 9 - 9 (1 bit)


MACFFR

Ethernet MAC frame filter register (ETH_MACCFFR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACFFR MACFFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PM HU HM DAIF PAM BFD PCF SAIF SAF HPF RA

PM : Promiscuous mode
bits : 0 - 0 (1 bit)

HU : Hash unicast
bits : 1 - 1 (1 bit)

HM : Hash multicast
bits : 2 - 2 (1 bit)

DAIF : Destination address inverse filtering
bits : 3 - 3 (1 bit)

PAM : Pass all multicast
bits : 4 - 4 (1 bit)

BFD : Broadcast frames disable
bits : 5 - 5 (1 bit)

PCF : Pass control frames
bits : 6 - 7 (2 bit)

SAIF : Source address inverse filtering
bits : 8 - 8 (1 bit)

SAF : Source address filter
bits : 9 - 9 (1 bit)

HPF : Hash or perfect filter
bits : 10 - 10 (1 bit)

RA : Receive all
bits : 31 - 31 (1 bit)


MACA0HR

Ethernet MAC address 0 high register (ETH_MACA0HR)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

MACA0HR MACA0HR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACA0H MO

MACA0H : MAC address0 high
bits : 0 - 15 (16 bit)
access : read-write

MO : Always 1
bits : 31 - 31 (1 bit)
access : read-only


MACA0LR

Ethernet MAC address 0 low register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA0LR MACA0LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACA0L

MACA0L : MAC address0 low
bits : 0 - 31 (32 bit)


MACA1HR

Ethernet MAC address 1 high register (ETH_MACA1HR)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA1HR MACA1HR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACA1H MBC SA AE

MACA1H : MAC address1 high
bits : 0 - 15 (16 bit)

MBC : Mask byte control
bits : 24 - 29 (6 bit)

SA : Source address
bits : 30 - 30 (1 bit)

AE : Address enable
bits : 31 - 31 (1 bit)


MACA1LR

Ethernet MAC address1 low register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA1LR MACA1LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACA1L

MACA1L : MAC address1 low
bits : 0 - 31 (32 bit)


MACA2HR

Ethernet MAC address 2 high register (ETH_MACA2HR)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA2HR MACA2HR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACA2HR MBC SA AE

ETH_MACA2HR : Ethernet MAC address 2 high register
bits : 0 - 15 (16 bit)

MBC : Mask byte control
bits : 24 - 29 (6 bit)

SA : Source address
bits : 30 - 30 (1 bit)

AE : Address enable
bits : 31 - 31 (1 bit)


MACA2LR

Ethernet MAC address 2 low register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA2LR MACA2LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACA2L

MACA2L : MAC address2 low
bits : 0 - 30 (31 bit)


MACA3HR

Ethernet MAC address 3 high register (ETH_MACA3HR)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA3HR MACA3HR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MACA3H MBC SA AE

MACA3H : MAC address3 high
bits : 0 - 15 (16 bit)

MBC : Mask byte control
bits : 24 - 29 (6 bit)

SA : Source address
bits : 30 - 30 (1 bit)

AE : Address enable
bits : 31 - 31 (1 bit)


MACA3LR

Ethernet MAC address 3 low register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACA3LR MACA3LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBCA3L

MBCA3L : MAC address3 low
bits : 0 - 31 (32 bit)


MACHTHR

Ethernet MAC hash table high register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACHTHR MACHTHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTH

HTH : Hash table high
bits : 0 - 31 (32 bit)


MACHTLR

Ethernet MAC hash table low register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACHTLR MACHTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTL

HTL : Hash table low
bits : 0 - 31 (32 bit)



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