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ETHERNET

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

MMCCR

MMCTIMR

MMCRIR

MMCTGFSCCR

MMCTGFMSCCR

MMCTGFCR

MMCTIR

MMCRFCECR

MMCRFAECR

MMCRIMR

MMCRGUFCR


MMCCR

Ethernet MMC control register (ETH_MMCCR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMCCR MMCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR CSR ROR MCF

CR : Counter reset
bits : 0 - 0 (1 bit)

CSR : Counter stop rollover
bits : 1 - 1 (1 bit)

ROR : Reset on read
bits : 2 - 2 (1 bit)

MCF : MMC counter freeze
bits : 31 - 31 (1 bit)


MMCTIMR

Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMCTIMR MMCTIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TGFSCM TGFMSCM TGFM

TGFSCM : Transmitted good frames single collision mask
bits : 14 - 14 (1 bit)

TGFMSCM : Transmitted good frames more single collision mask
bits : 15 - 15 (1 bit)

TGFM : Transmitted good frames mask
bits : 21 - 21 (1 bit)


MMCRIR

Ethernet MMC receive interrupt register (ETH_MMCRIR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMCRIR MMCRIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCES RFAES RGUFS

RFCES : Received frames CRC error status
bits : 5 - 5 (1 bit)

RFAES : Received frames alignment error status
bits : 6 - 6 (1 bit)

RGUFS : Received Good Unicast Frames Status
bits : 17 - 17 (1 bit)


MMCTGFSCCR

Ethernet MMC transmitted good frames after a single collision counter
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMCTGFSCCR MMCTGFSCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TGFSCC

TGFSCC : Transmitted good frames after a single collision counter
bits : 0 - 31 (32 bit)


MMCTGFMSCCR

Ethernet MMC transmitted good frames after more than a single collision
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMCTGFMSCCR MMCTGFMSCCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TGFMSCC

TGFMSCC : Transmitted good frames after more than a single collision counter
bits : 0 - 31 (32 bit)


MMCTGFCR

Ethernet MMC transmitted good frames counter register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMCTGFCR MMCTGFCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TGFC

TGFC : Transmitted good frames counter
bits : 0 - 31 (32 bit)


MMCTIR

Ethernet MMC transmit interrupt register (ETH_MMCTIR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMCTIR MMCTIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TGFSCS TGFMSCS TGFS

TGFSCS : Transmitted good frames single collision status
bits : 14 - 14 (1 bit)

TGFMSCS : Transmitted good frames more single collision status
bits : 15 - 15 (1 bit)

TGFS : Transmitted good frames status
bits : 21 - 21 (1 bit)


MMCRFCECR

Ethernet MMC received frames with CRC error counter register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMCRFCECR MMCRFCECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCFC

RFCFC : Received frames with CRC error counter
bits : 0 - 31 (32 bit)


MMCRFAECR

Ethernet MMC received frames with alignment error counter register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMCRFAECR MMCRFAECR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFAEC

RFAEC : Received frames with alignment error counter
bits : 0 - 31 (32 bit)


MMCRIMR

Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMCRIMR MMCRIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCEM RFAEM RGUFM

RFCEM : Received frame CRC error mask
bits : 5 - 5 (1 bit)

RFAEM : Received frames alignment error mask
bits : 6 - 6 (1 bit)

RGUFM : Received good unicast frames mask
bits : 17 - 17 (1 bit)


MMCRGUFCR

MMC received good unicast frames counter register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMCRGUFCR MMCRGUFCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGUFC

RGUFC : Received good unicast frames counter
bits : 0 - 31 (32 bit)



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