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ETHERNET

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

DMABMR

DMATDLAR

DMASR

DMAOMR

DMAIER

DMAMFBOCR

DMATPDR

DMACHTDR

DMACHRDR

DMACHTBAR

DMACHRBAR

DMARPDR

DMARDLAR


DMABMR

Ethernet DMA bus mode register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMABMR DMABMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR DA DSL PBL RTPR FB RDP USP FPM AAB

SR : Software reset
bits : 0 - 0 (1 bit)

DA : DMA Arbitration
bits : 1 - 1 (1 bit)

DSL : Descriptor skip length
bits : 2 - 6 (5 bit)

PBL : Programmable burst length
bits : 8 - 13 (6 bit)

RTPR : Rx Tx priority ratio
bits : 14 - 15 (2 bit)

FB : Fixed burst
bits : 16 - 16 (1 bit)

RDP : Rx DMA PBL
bits : 17 - 22 (6 bit)

USP : Use separate PBL
bits : 23 - 23 (1 bit)

FPM : 4xPBL mode
bits : 24 - 24 (1 bit)

AAB : Address-aligned beats
bits : 25 - 25 (1 bit)


DMATDLAR

Ethernet DMA transmit descriptor list address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATDLAR DMATDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STL

STL : Start of transmit list
bits : 0 - 31 (32 bit)


DMASR

Ethernet DMA status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

DMASR DMASR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS TPSS TBUS TJTS ROS TUS RS RBUS RPSS PWTS ETS FBES ERS AIS NIS RPS TPS EBS MMCS PMTS TSTS IPLS

TS : Transmit status
bits : 0 - 0 (1 bit)
access : read/clear

TPSS : Transmit process stopped status
bits : 1 - 1 (1 bit)
access : read/clear

TBUS : Transmit buffer unavailable status
bits : 2 - 2 (1 bit)
access : read/clear

TJTS : Transmit jabber timeout status
bits : 3 - 3 (1 bit)
access : read/clear

ROS : Receive overflow status
bits : 4 - 4 (1 bit)
access : read/clear

TUS : Transmit underflow status
bits : 5 - 5 (1 bit)
access : read/clear

RS : Receive status
bits : 6 - 6 (1 bit)
access : read/clear

RBUS : Receive buffer unavailable status
bits : 7 - 7 (1 bit)
access : read/clear

RPSS : Receive process stopped status
bits : 8 - 8 (1 bit)
access : read/clear

PWTS : Receive watchdog timeout status
bits : 9 - 9 (1 bit)
access : read/clear

ETS : Early transmit status
bits : 10 - 10 (1 bit)
access : read/clear

FBES : Fatal bus error status
bits : 13 - 13 (1 bit)
access : read/clear

ERS : Early receive status
bits : 14 - 14 (1 bit)
access : read/clear

AIS : Abnormal interrupt summary
bits : 15 - 15 (1 bit)
access : read/clear

NIS : Normal interrupt summary
bits : 16 - 16 (1 bit)
access : read/clear

RPS : Receive process state
bits : 17 - 19 (3 bit)
access : read-only

TPS : Transmit process state
bits : 20 - 22 (3 bit)
access : read-only

EBS : Error bits status
bits : 23 - 25 (3 bit)
access : read-only

MMCS : MMC status
bits : 27 - 27 (1 bit)
access : read-only

PMTS : PMT status
bits : 28 - 28 (1 bit)
access : read-only

TSTS : Time stamp trigger status
bits : 29 - 29 (1 bit)
access : read-only

IPLS : 10MPHY Physical layer variation
bits : 31 - 31 (1 bit)
access : read-only


DMAOMR

Ethernet DMA operation mode register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAOMR DMAOMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR OSF RTC FUGF FEF ST TTC FTF TSF DFRF RSF DTCEFD

SR : SR
bits : 1 - 1 (1 bit)

OSF : OSF
bits : 2 - 2 (1 bit)

RTC : RTC
bits : 3 - 4 (2 bit)

FUGF : FUGF
bits : 6 - 6 (1 bit)

FEF : FEF
bits : 7 - 7 (1 bit)

ST : ST
bits : 13 - 13 (1 bit)

TTC : TTC
bits : 14 - 16 (3 bit)

FTF : FTF
bits : 20 - 20 (1 bit)

TSF : TSF
bits : 21 - 21 (1 bit)

DFRF : DFRF
bits : 24 - 24 (1 bit)

RSF : RSF
bits : 25 - 25 (1 bit)

DTCEFD : DTCEFD
bits : 26 - 26 (1 bit)


DMAIER

Ethernet DMA interrupt enable register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAIER DMAIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE TPSIE TBUIE TJTIE ROIE TUIE RIE RBUIE RPSIE RWTIE ETIE FBEIE ERIE AISE NISE IPLE

TIE : Transmit interrupt enable
bits : 0 - 0 (1 bit)

TPSIE : Transmit process stopped interrupt enable
bits : 1 - 1 (1 bit)

TBUIE : Transmit buffer unavailable interrupt enable
bits : 2 - 2 (1 bit)

TJTIE : Transmit jabber timeout interrupt enable
bits : 3 - 3 (1 bit)

ROIE : Overflow interrupt enable
bits : 4 - 4 (1 bit)

TUIE : Underflow interrupt enable
bits : 5 - 5 (1 bit)

RIE : Receive interrupt enable
bits : 6 - 6 (1 bit)

RBUIE : Receive buffer unavailable interrupt enable
bits : 7 - 7 (1 bit)

RPSIE : Receive process stopped interrupt enable
bits : 8 - 8 (1 bit)

RWTIE : receive watchdog timeout interrupt enable
bits : 9 - 9 (1 bit)

ETIE : Early transmit interrupt enable
bits : 10 - 10 (1 bit)

FBEIE : Fatal bus error interrupt enable
bits : 13 - 13 (1 bit)

ERIE : Early receive interrupt enable
bits : 14 - 14 (1 bit)

AISE : Abnormal interrupt summary enable
bits : 15 - 15 (1 bit)

NISE : Normal interrupt summary enable
bits : 16 - 16 (1 bit)

IPLE : 10M Physical layer connection
bits : 31 - 31 (1 bit)


DMAMFBOCR

Ethernet DMA missed frame and buffer overflow counter register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAMFBOCR DMAMFBOCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MFC OMFC MFA OFOC

MFC : Missed frames by the controller
bits : 0 - 15 (16 bit)

OMFC : Overflow bit for missed frame counter
bits : 16 - 16 (1 bit)

MFA : Missed frames by the application
bits : 17 - 27 (11 bit)

OFOC : Overflow bit for FIFO overflow counter
bits : 28 - 28 (1 bit)


DMATPDR

Ethernet DMA transmit poll demand register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMATPDR DMATPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPD

TPD : Transmit poll demand
bits : 0 - 31 (32 bit)


DMACHTDR

Ethernet DMA current host transmit descriptor register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACHTDR DMACHTDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTDAP

HTDAP : Host transmit descriptor address pointer
bits : 0 - 31 (32 bit)


DMACHRDR

Ethernet DMA current host receive descriptor register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACHRDR DMACHRDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRDAP

HRDAP : Host receive descriptor address pointer
bits : 0 - 31 (32 bit)


DMACHTBAR

Ethernet DMA current host transmit buffer address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACHTBAR DMACHTBAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTBAP

HTBAP : Host transmit buffer address pointer
bits : 0 - 31 (32 bit)


DMACHRBAR

Ethernet DMA current host receive buffer address register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMACHRBAR DMACHRBAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HRBAP

HRBAP : Host receive buffer address pointer
bits : 0 - 31 (32 bit)


DMARPDR

EHERNET DMA receive poll demand register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMARPDR DMARPDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPD

RPD : Receive poll demand
bits : 0 - 31 (32 bit)


DMARDLAR

Ethernet DMA receive descriptor list address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMARDLAR DMARDLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRL

SRL : Start of receive list
bits : 0 - 31 (32 bit)



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