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SDIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

POWER

RESPCMD

RESP1

RESP2

RESP3

RESP4

DTIMER

DLEN

DCTRL

DCOUNT

STA

ICR

MASK

CLKCR

FIFOCNT

ARG

FIFO

CMD


POWER

Bits 1:0 = PWRCTRL: Power supply control bits
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER POWER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRCTRL

PWRCTRL : Power supply control bits
bits : 0 - 1 (2 bit)


RESPCMD

SDIO command register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESPCMD RESPCMD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPCMD

RESPCMD : Response command index
bits : 0 - 5 (6 bit)


RESP1

Bits 31:0 = CARDSTATUS1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESP1 RESP1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS1

CARDSTATUS1 : Card status 1
bits : 0 - 31 (32 bit)


RESP2

Bits 31:0 = CARDSTATUS2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESP2 RESP2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS2

CARDSTATUS2 : Card status 2
bits : 0 - 31 (32 bit)


RESP3

Bits 31:0 = CARDSTATUS3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESP3 RESP3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS3

CARDSTATUS3 : Card status 3
bits : 0 - 31 (32 bit)


RESP4

Bits 31:0 = CARDSTATUS4
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESP4 RESP4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CARDSTATUS4

CARDSTATUS4 : Card status 4
bits : 0 - 31 (32 bit)


DTIMER

Bits 31:0 = DATATIME: Data timeout period
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTIMER DTIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATIME

DATATIME : Data timeout period
bits : 0 - 31 (32 bit)


DLEN

Bits 24:0 = DATALENGTH: Data length value
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLEN DLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATALENGTH

DATALENGTH : Data length value
bits : 0 - 24 (25 bit)


DCTRL

SDIO data control register (SDIO_DCTRL)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTRL DCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTEN DTDIR DTMODE DMAEN DBLOCKSIZE PWSTART PWSTOP RWMOD SDIOEN

DTEN : Data transfer enabled bit
bits : 0 - 0 (1 bit)

DTDIR : Data transfer direction selection
bits : 1 - 1 (1 bit)

DTMODE : Data transfer mode selection 1: Stream or SDIO multibyte data transfer
bits : 2 - 2 (1 bit)

DMAEN : DMA enable bit
bits : 3 - 3 (1 bit)

DBLOCKSIZE : Data block size
bits : 4 - 7 (4 bit)

PWSTART : Read wait start
bits : 8 - 8 (1 bit)

PWSTOP : Read wait stop
bits : 9 - 9 (1 bit)

RWMOD : Read wait mode
bits : 10 - 10 (1 bit)

SDIOEN : SD I/O enable functions
bits : 11 - 11 (1 bit)


DCOUNT

Bits 24:0 = DATACOUNT: Data count value
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCOUNT DCOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATACOUNT

DATACOUNT : Data count value
bits : 0 - 24 (25 bit)


STA

SDIO status register (SDIO_STA)
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STA STA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCRCFAIL DCRCFAIL CTIMEOUT DTIMEOUT TXUNDERR RXOVERR CMDREND CMDSENT DATAEND STBITERR DBCKEND CMDACT TXACT RXACT TXFIFOHE RXFIFOHF TXFIFOF RXFIFOF TXFIFOE RXFIFOE TXDAVL RXDAVL SDIOIT CEATAEND

CCRCFAIL : Command response received (CRC check failed)
bits : 0 - 0 (1 bit)

DCRCFAIL : Data block sent/received (CRC check failed)
bits : 1 - 1 (1 bit)

CTIMEOUT : Command response timeout
bits : 2 - 2 (1 bit)

DTIMEOUT : Data timeout
bits : 3 - 3 (1 bit)

TXUNDERR : Transmit FIFO underrun error
bits : 4 - 4 (1 bit)

RXOVERR : Received FIFO overrun error
bits : 5 - 5 (1 bit)

CMDREND : Command response received (CRC check passed)
bits : 6 - 6 (1 bit)

CMDSENT : Command sent (no response required)
bits : 7 - 7 (1 bit)

DATAEND : Data end (data counter, SDIDCOUNT, is zero)
bits : 8 - 8 (1 bit)

STBITERR : Start bit not detected on all data signals in wide bus mode
bits : 9 - 9 (1 bit)

DBCKEND : Data block sent/received (CRC check passed)
bits : 10 - 10 (1 bit)

CMDACT : Command transfer in progress
bits : 11 - 11 (1 bit)

TXACT : Data transmit in progress
bits : 12 - 12 (1 bit)

RXACT : Data receive in progress
bits : 13 - 13 (1 bit)

TXFIFOHE : Transmit FIFO half empty: at least 8 words can be written into the FIFO
bits : 14 - 14 (1 bit)

RXFIFOHF : Receive FIFO half full: there are at least 8 words in the FIFO
bits : 15 - 15 (1 bit)

TXFIFOF : Transmit FIFO full
bits : 16 - 16 (1 bit)

RXFIFOF : Receive FIFO full
bits : 17 - 17 (1 bit)

TXFIFOE : Transmit FIFO empty
bits : 18 - 18 (1 bit)

RXFIFOE : Receive FIFO empty
bits : 19 - 19 (1 bit)

TXDAVL : Data available in transmit FIFO
bits : 20 - 20 (1 bit)

RXDAVL : Data available in receive FIFO
bits : 21 - 21 (1 bit)

SDIOIT : SDIO interrupt received
bits : 22 - 22 (1 bit)

CEATAEND : CE-ATA command completion signal received for CMD61
bits : 23 - 23 (1 bit)


ICR

SDIO interrupt clear register (SDIO_ICR)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCRCFAILC DCRCFAILC CTIMEOUTC DTIMEOUTC TXUNDERRC RXOVERRC CMDRENDC CMDSENTC DATAENDC STBITERRC DBCKENDC SDIOITC CEATAENDC

CCRCFAILC : CCRCFAIL flag clear bit
bits : 0 - 0 (1 bit)

DCRCFAILC : DCRCFAIL flag clear bit
bits : 1 - 1 (1 bit)

CTIMEOUTC : CTIMEOUT flag clear bit
bits : 2 - 2 (1 bit)

DTIMEOUTC : DTIMEOUT flag clear bit
bits : 3 - 3 (1 bit)

TXUNDERRC : TXUNDERR flag clear bit
bits : 4 - 4 (1 bit)

RXOVERRC : RXOVERR flag clear bit
bits : 5 - 5 (1 bit)

CMDRENDC : CMDREND flag clear bit
bits : 6 - 6 (1 bit)

CMDSENTC : CMDSENT flag clear bit
bits : 7 - 7 (1 bit)

DATAENDC : DATAEND flag clear bit
bits : 8 - 8 (1 bit)

STBITERRC : STBITERR flag clear bit
bits : 9 - 9 (1 bit)

DBCKENDC : DBCKEND flag clear bit
bits : 10 - 10 (1 bit)

SDIOITC : SDIOIT flag clear bit
bits : 22 - 22 (1 bit)

CEATAENDC : CEATAEND flag clear bit
bits : 23 - 23 (1 bit)


MASK

SDIO mask register (SDIO_MASK)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASK MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCRCFAILIE DCRCFAILIE CTIMEOUTIE DTIMEOUTIE TXUNDERRIE RXOVERRIE CMDRENDIE CMDSENTIE DATAENDIE STBITERRIE DBACKENDIE CMDACTIE TXACTIE RXACTIE TXFIFOHEIE RXFIFOHFIE TXFIFOFIE RXFIFOFIE TXFIFOEIE RXFIFOEIE TXDAVLIE RXDAVLIE SDIOITIE CEATENDIE

CCRCFAILIE : Command CRC fail interrupt enable
bits : 0 - 0 (1 bit)

DCRCFAILIE : Data CRC fail interrupt enable
bits : 1 - 1 (1 bit)

CTIMEOUTIE : Command timeout interrupt enable
bits : 2 - 2 (1 bit)

DTIMEOUTIE : Data timeout interrupt enable
bits : 3 - 3 (1 bit)

TXUNDERRIE : Tx FIFO underrun error interrupt enable
bits : 4 - 4 (1 bit)

RXOVERRIE : Rx FIFO overrun error interrupt enable
bits : 5 - 5 (1 bit)

CMDRENDIE : Command response received interrupt enable
bits : 6 - 6 (1 bit)

CMDSENTIE : Command sent interrupt enable
bits : 7 - 7 (1 bit)

DATAENDIE : Data end interrupt enable
bits : 8 - 8 (1 bit)

STBITERRIE : Start bit error interrupt enable
bits : 9 - 9 (1 bit)

DBACKENDIE : Data block end interrupt enable
bits : 10 - 10 (1 bit)

CMDACTIE : Command acting interrupt enable
bits : 11 - 11 (1 bit)

TXACTIE : Data transmit acting interrupt enable
bits : 12 - 12 (1 bit)

RXACTIE : Data receive acting interrupt enable
bits : 13 - 13 (1 bit)

TXFIFOHEIE : Tx FIFO half empty interrupt enable
bits : 14 - 14 (1 bit)

RXFIFOHFIE : Rx FIFO half full interrupt enable
bits : 15 - 15 (1 bit)

TXFIFOFIE : Tx FIFO full interrupt enable
bits : 16 - 16 (1 bit)

RXFIFOFIE : Rx FIFO full interrupt enable
bits : 17 - 17 (1 bit)

TXFIFOEIE : Tx FIFO empty interrupt enable
bits : 18 - 18 (1 bit)

RXFIFOEIE : Rx FIFO empty interrupt enable
bits : 19 - 19 (1 bit)

TXDAVLIE : Data available in Tx FIFO interrupt enable
bits : 20 - 20 (1 bit)

RXDAVLIE : Data available in Rx FIFO interrupt enable
bits : 21 - 21 (1 bit)

SDIOITIE : SDIO mode interrupt received interrupt enable
bits : 22 - 22 (1 bit)

CEATENDIE : CE-ATA command completion signal received interrupt enable
bits : 23 - 23 (1 bit)


CLKCR

SDI clock control register (SDIO_CLKCR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCR CLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDIV CLKEN PWRSAV BYPASS WIDBUS NEGEDGE HWFC_EN

CLKDIV : Clock divide factor
bits : 0 - 7 (8 bit)

CLKEN : Clock enable bit
bits : 8 - 8 (1 bit)

PWRSAV : Power saving configuration bit
bits : 9 - 9 (1 bit)

BYPASS : Clock divider bypass enable bit
bits : 10 - 10 (1 bit)

WIDBUS : Wide bus mode enable bit
bits : 11 - 12 (2 bit)

NEGEDGE : SDIO_CK dephasing selection bit
bits : 13 - 13 (1 bit)

HWFC_EN : HW Flow Control enable
bits : 14 - 14 (1 bit)


FIFOCNT

Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFOCNT FIFOCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIF0COUNT

FIF0COUNT : Remaining number of words to be written to or read from the FIFO
bits : 0 - 31 (32 bit)


ARG

Bits 31:0 = : Command argument
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARG ARG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDARG

CMDARG : Command argument
bits : 0 - 31 (32 bit)


FIFO

bits 31:0 = FIFOData: Receive and transmit FIFO data
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFOData

FIFOData : Receive and transmit FIFO data
bits : 0 - 31 (32 bit)


CMD

SDIO command register (SDIO_CMD)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDINDEX WAITRESP WAITINT WAITPEND CPSMEN SDIOSuspend ENCMDcompl nIEN CE_ATACMD

CMDINDEX : Command index
bits : 0 - 5 (6 bit)

WAITRESP : Wait for response bits
bits : 6 - 7 (2 bit)

WAITINT : CPSM waits for interrupt request
bits : 8 - 8 (1 bit)

WAITPEND : CPSM Waits for ends of data transfer (CmdPend internal signal)
bits : 9 - 9 (1 bit)

CPSMEN : Command path state machine (CPSM) Enable bit
bits : 10 - 10 (1 bit)

SDIOSuspend : SD I/O suspend command
bits : 11 - 11 (1 bit)

ENCMDcompl : Enable CMD completion
bits : 12 - 12 (1 bit)

nIEN : not Interrupt Enable
bits : 13 - 13 (1 bit)

CE_ATACMD : CE-ATA command
bits : 14 - 14 (1 bit)



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