\n

FSMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

BCR1

BWTR1

BTR1

PCR2

SR2

PMEM2

PATT2

ECCR2


BCR1

SRAM/NOR-Flash chip-select control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCR1 BCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBKEN MUXEN MTYP MWID FACCEN BURSTEN WAITPOL WRAPMOD WAITCFG WREN WAITEN EXTMOD ASYNCWAIT CBURSTRW

MBKEN : Memory bank enable bit
bits : 0 - 0 (1 bit)
access : read-write

MUXEN : Address/data multiplexing enable bit
bits : 1 - 1 (1 bit)
access : read-write

MTYP : Memory type
bits : 2 - 3 (2 bit)
access : read-write

MWID : Memory databus width
bits : 4 - 5 (2 bit)
access : read-write

FACCEN : Flash access enable
bits : 6 - 6 (1 bit)
access : read-write

BURSTEN : Burst enable bit
bits : 8 - 8 (1 bit)
access : read-write

WAITPOL : Wait signal polarity bit
bits : 9 - 9 (1 bit)
access : read-write

WRAPMOD : Wrapped burst mode support
bits : 10 - 10 (1 bit)
access : read-write

WAITCFG : Wait timing configuration
bits : 11 - 11 (1 bit)
access : read-write

WREN : Write enable bit
bits : 12 - 12 (1 bit)
access : read-write

WAITEN : Wait enable bit
bits : 13 - 13 (1 bit)
access : read-write

EXTMOD : Extended mode enable
bits : 14 - 14 (1 bit)
access : read-write

ASYNCWAIT : Wait signal during asynchronous transfers
bits : 15 - 15 (1 bit)
access : read-write

CBURSTRW : Write burst enable
bits : 19 - 19 (1 bit)
access : read-write


BWTR1

SRAM/NOR-Flash write timing registers 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BWTR1 BWTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST CLKDIV DATLAT ACCMOD

ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)

ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)

DATAST : Data-phase duration
bits : 8 - 15 (8 bit)

CLKDIV : Clock divide ratio (for FSMC_CLK signal)
bits : 20 - 23 (4 bit)

DATLAT : Data latency for synchronous NOR Flash memory
bits : 24 - 27 (4 bit)

ACCMOD : Access mode
bits : 28 - 29 (2 bit)


BTR1

SRAM/NOR-Flash chip-select timing register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BTR1 BTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDSET ADDHLD DATAST BUSTURN CLKDIV DATLAT ACCMOD

ADDSET : Address setup phase duration
bits : 0 - 3 (4 bit)
access : read-write

ADDHLD : Address-hold phase duration
bits : 4 - 7 (4 bit)
access : read-write

DATAST : Data-phase duration
bits : 8 - 15 (8 bit)
access : read-write

BUSTURN : Bus turnaround phase duration
bits : 16 - 19 (4 bit)
access : read-write

CLKDIV : Clock divide ratio (for FSMC_CLK signal)
bits : 20 - 23 (4 bit)
access : read-write

DATLAT : Data latency for synchronous NOR Flash memory
bits : 24 - 27 (4 bit)
access : read-write

ACCMOD : Access mode
bits : 28 - 29 (2 bit)
access : read-write


PCR2

PC Card/NAND Flash control register 2
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR2 PCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWAITEN PBKEN PTYP PWID ECCEN TCLR TAR ECCPS

PWAITEN : Wait feature enable bit
bits : 1 - 1 (1 bit)

PBKEN : PC Card/NAND Flash memory bank enable bit
bits : 2 - 2 (1 bit)

PTYP : Memory type
bits : 3 - 3 (1 bit)

PWID : Databus width
bits : 4 - 5 (2 bit)

ECCEN : ECC computation logic enable bit
bits : 6 - 6 (1 bit)

TCLR : CLE to RE delay
bits : 9 - 12 (4 bit)

TAR : ALE to RE delay
bits : 13 - 16 (4 bit)

ECCPS : ECC page size
bits : 17 - 19 (3 bit)


SR2

FIFO status and interrupt register 2
address_offset : 0x64 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRS ILS IFS IREN ILEN IFEN FEMPT

IRS : Interrupt rising edge status
bits : 0 - 0 (1 bit)
access : read-write

ILS : Interrupt high-level status
bits : 1 - 1 (1 bit)
access : read-write

IFS : Interrupt falling edge status
bits : 2 - 2 (1 bit)
access : read-write

IREN : Interrupt rising edge detection enable bit
bits : 3 - 3 (1 bit)
access : read-write

ILEN : Interrupt high-level detection enable bit
bits : 4 - 4 (1 bit)
access : read-write

IFEN : Interrupt falling edge detection enable bit
bits : 5 - 5 (1 bit)
access : read-write

FEMPT : FIFO empty
bits : 6 - 6 (1 bit)
access : read-only


PMEM2

Common memory space timing register 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMEM2 PMEM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMSETx MEMWAITx MEMHOLDx MEMHIZx

MEMSETx : Common memory x setup time
bits : 0 - 7 (8 bit)

MEMWAITx : Common memory x wait time
bits : 8 - 15 (8 bit)

MEMHOLDx : Common memory x hold time
bits : 16 - 23 (8 bit)

MEMHIZx : Common memory x databus HiZ time
bits : 24 - 31 (8 bit)


PATT2

Attribute memory space timing register 2
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATT2 PATT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATTSETx ATTWAITx ATTHOLDx ATTHIZx

ATTSETx : Attribute memory x setup time
bits : 0 - 7 (8 bit)

ATTWAITx : Attribute memory x wait time
bits : 8 - 15 (8 bit)

ATTHOLDx : Attribute memory x hold time
bits : 16 - 23 (8 bit)

ATTHIZx : Attribute memory x databus HiZ time
bits : 24 - 31 (8 bit)


ECCR2

ECC result register 2
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECCR2 ECCR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECCx

ECCx : ECC result
bits : 0 - 31 (32 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.