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DVP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR0

CR1

IFR

STATUS

ROW_CNT

HOFFCNT

VST

CAPCNT

VLINE

IER

DR

ROW_NUM

COL_NUM

DMA_BUF0

DMA_BUF1


CR0

Digital Video control register (DVP_CR0)
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_ENABLE RB_DVP_V_POLAR RB_DVP_H_POLAR RB_DVP_P_POLAR RB_DVP_MSK_DAT_MOD RB_DVP_JPEG

RB_DVP_ENABLE : DVP enable
bits : 0 - 0 (1 bit)
access : read-write

RB_DVP_V_POLAR : DVP VSYNC polarity control
bits : 1 - 1 (1 bit)
access : read-write

RB_DVP_H_POLAR : DVP HSYNC polarity control
bits : 2 - 2 (1 bit)
access : read-write

RB_DVP_P_POLAR : DVP PCLK polarity control
bits : 3 - 3 (1 bit)
access : read-write

RB_DVP_MSK_DAT_MOD : DVP data mode
bits : 4 - 5 (2 bit)

RB_DVP_JPEG : DVP JPEG mode
bits : 6 - 6 (1 bit)
access : read-write


CR1

Digital Video control register (DVP_CR1)
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_DMA_EN RB_DVP_ALL_CLR RB_DVP_RCV_CLR RB_DVP_BUF_TOG RB_DVP_CM RB_DVP_CROP RB_DVP_FCRC

RB_DVP_DMA_EN : DVP dma enable
bits : 0 - 0 (1 bit)
access : read-write

RB_DVP_ALL_CLR : DVP all clear
bits : 1 - 1 (1 bit)
access : read-write

RB_DVP_RCV_CLR : DVP receive logic clear
bits : 2 - 2 (1 bit)
access : read-write

RB_DVP_BUF_TOG : DVP bug toggle by software
bits : 3 - 3 (1 bit)
access : read-write

RB_DVP_CM : DVP capture mode
bits : 4 - 4 (1 bit)
access : read-write

RB_DVP_CROP : DVP Crop feature enable
bits : 5 - 5 (1 bit)
access : read-write

RB_DVP_FCRC : DVP frame capture rate control
bits : 6 - 7 (2 bit)
access : read-write


IFR

Digital Video Flag register (DVP_IFR)
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFR IFR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_IF_STR_FRM RB_DVP_IF_ROW_DONE RB_DVP_IF_FRM_DONE RB_DVP_IF_FIFO_OV RB_DVP_IF_STP_FRM

RB_DVP_IF_STR_FRM : DVP frame start interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

RB_DVP_IF_ROW_DONE : DVP row received done interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

RB_DVP_IF_FRM_DONE : DVP frame received done interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

RB_DVP_IF_FIFO_OV : DVP receive fifo overflow interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

RB_DVP_IF_STP_FRM : DVP frame stop interrupt enable
bits : 4 - 4 (1 bit)
access : read-write


STATUS

Digital Video STATUS register (DVP_STATUS)
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_FIFO_RDY RB_DVP_FIFO_FULL RB_DVP_FIFO_OV RB_DVP_MSK_FIFO_CNT

RB_DVP_FIFO_RDY : DVP frame start interrupt enable
bits : 0 - 0 (1 bit)
access : read-only

RB_DVP_FIFO_FULL : DVP row received done interrupt enable
bits : 1 - 1 (1 bit)
access : read-only

RB_DVP_FIFO_OV : DVP frame received done interrupt enable
bits : 2 - 2 (1 bit)
access : read-only

RB_DVP_MSK_FIFO_CNT : DVP receive fifo overflow interrupt enable
bits : 4 - 6 (3 bit)
access : read-only


ROW_CNT

Digital Video line counter register (DVP_ROW_CNT)
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ROW_CNT ROW_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_ROW_CNT

RB_DVP_ROW_CNT : The number of rows of frame image data
bits : 0 - 15 (16 bit)
access : read-only


HOFFCNT

Digital Video horizontal displacement register (DVP_HOFFCNT)
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOFFCNT HOFFCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_HOFFCNT

RB_DVP_HOFFCNT : Number of PCLK cycles for row data
bits : 0 - 15 (16 bit)
access : read-write


VST

Digital Video line number register (DVP_VST)
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VST VST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_VST

RB_DVP_VST : The number of lines captured by the image
bits : 0 - 15 (16 bit)
access : read-write


CAPCNT

Digital Video Capture count register (DVP_CAPCNT)
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPCNT CAPCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_CAPCNT

RB_DVP_CAPCNT : Number of PCLK cycles captured by clipping window
bits : 0 - 15 (16 bit)
access : read-write


VLINE

Digital Video Vertical line count register (DVP_VLINE)
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VLINE VLINE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_VLINE

RB_DVP_VLINE : Crop the number of rows captured by window
bits : 0 - 15 (16 bit)
access : read-write


IER

Digital Video Interrupt register (DVP_IER)
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_IE_STR_FRM RB_DVP_IE_ROW_DONE RB_DVP_IE_FRM_DONE RB_DVP_IE_FIFO_OV RB_DVP_IE_STP_FRM

RB_DVP_IE_STR_FRM : DVP frame start interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

RB_DVP_IE_ROW_DONE : DVP row received done interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

RB_DVP_IE_FRM_DONE : DVP frame received done interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

RB_DVP_IE_FIFO_OV : DVP receive fifo overflow interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

RB_DVP_IE_STP_FRM : DVP frame stop interrupt enable
bits : 4 - 4 (1 bit)
access : read-write


DR

Digital Video Data register (DVP_DR)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_DR

RB_DVP_DR : Prevent DMA overflow
bits : 0 - 31 (32 bit)


ROW_NUM

Image line count configuration register (DVP_ROW_NUM)
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROW_NUM ROW_NUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_ROW_NUM

RB_DVP_ROW_NUM : The number of rows of frame image data
bits : 0 - 15 (16 bit)
access : read-write


COL_NUM

Image column number configuration register (DVP_COL_NUM)
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COL_NUM COL_NUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_COL_NUM

RB_DVP_COL_NUM : Number of PCLK cycles for row data
bits : 0 - 15 (16 bit)
access : read-write


DMA_BUF0

Digital Video DMA address register (DVP_DMA_BUF0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_BUF0 DMA_BUF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_DMA_BUF0

RB_DVP_DMA_BUF0 : DMA receive address 0
bits : 0 - 16 (17 bit)
access : read-write


DMA_BUF1

Digital Video DMA address register (DVP_DMA_BUF1)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_BUF1 DMA_BUF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_DMA_BUF1

RB_DVP_DMA_BUF1 : DMA receive address 1
bits : 0 - 16 (17 bit)
access : read-write



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